- Nov 6, 2018
Sure looks like Real ASP's are way way higher on Instinct than even Epyc. That's why it was first.
The biggest reason to go monolithic on desktop is DRAM latency -- since they are using lines on organic package, they will have to use SerDes, and that always costs a few cycles. For servers, the unified memory space is worth losing a little bit on latency, but on desktop, especially in games, it still hurts.
Even given that, I honestly think that it's quite unlikely that there would be 3 separate 7nm Zen2 dies. Aside from the chiplet for EPYC and TR, I think that an APU die is possible, but I honestly think it would be unlikely that there would be a separate one for >8 core Ryzen. Either entire non-HEDT market is served from the APU chip, or there is a separate IO chip that gets paired with 2 cpu chiplets.
As we know, there are at least two version of TSMC's 7 nm process. Cheaper process for mobile SoCs and more expensive one for HPC. Let's call them 7FF and 7HPC as stated here. My question is that would AMD use solely 7HPC or would they use 7FF for lower end parts? Like this:
- Picasso (Edit: Renoir), 7FF (Edit: 7HPC), low cost, low power, medium clocks
- Matisse, 7HPC, higher cost, low enough/medium power, high clocks
- Rome / TR3 chiplet, 7HPC, higher cost, power scalability, medium (good perf/W) or high clocks (absolute performance)
- Rome / TR3 IO die, 14HP (???), higher cost, high amount of cache / buffers (eDRAM) for mitigating latency issues
So, reading that, would it mean that a console APU has to be monolithic? Mainly for latency reasons?
Also I have been thinking that maybe the next-gen consoles will have 6C CCX (or 2 x 3C CCX, although the latter might not be that good of a solution but still much better than 8 Jaguars cores). Then AMD could use that same 6C setup for their APU. Matisse could either use 3 x 4C CCX or 2 x 6C CCX if those were the options or it could be just 8 cores with a lot of L3 (and/or maybe some kind of chiplet design with smaller IOD as many seem to suggest).
Then there is Navi. Is AMD going to use 7HPC here or is 7FF (Edit: no 7FF for Navi either) good enough? I'm guessing it depends on many things like yields and performance of 7FF. If 7FF is much cheaper or Samsung will have a cheaper alternative then maybe APUs and even Navi could be manufactured there. I'm guessing, that it won't be a huge chip. If anyone has any better knowledge or even some good guesses, let us know.
Also if AMD would use many different 7 nm processes, it might not be so easy to port different IP and designs between e.g. 7FF and 7HPC.
It's very limiting for consoles to use monolithic designs and you could always leave memory controllers on a separate die and connect GPU using a high speed link to that. The GPU could even have a one stack of HBM2 memory as a cache but that might still be a too expensive solution for console purposes. There are a lot of benefits going for MCM like designs but HBM would always require either a silicon interposer or an EMIB-like solutiion.
I'm guessing that Kaby Lake G has some (or most) of the elements we would like to see in future AMD APU (namely HBM2 memory and MCM design). Even Intel can't currently sell Kaby Lake G as a low end part , though.
- Show all