A brief history of time ...
Historically, in x86 architecture computers starting with the very first IBM PC, RAM grew from the bottom up and I/O grew from the top down. This model is imposed by the processor, which fetches its first instruction from the very top of its address space - which means that as a system designer, you need to put the firmware ROM up there, else the thing won't start.
The IBM PC had 20-bit addressing, which gave 1 MByte. I/O occupied the space from 640K-1M with the ROM at the top and some space for expansion cards below it, and as we all know, this meant you could have 640K of RAM.
The next generation, the PC-AT, with the new 286 processor that added four address bits to give 16 MBytes of address space. This was exclusively used for "extended RAM", while the I/O hole was not relocated to below-16M to keep the PC-AT software compatible with its predecessors. [Insert mandatory GateA20 rant here]. The 286 was special in that it fetched its first instruction still from 1M-16, not from 16M-16, so there was no I/O hole below 16M (until "linear mode" ISA VGA cards made their brief appearance, but let's skip that for now).
Then came the 386, with 32-bit addressing. This one did fetch its first instruction from 4G-16, and thus required the BIOS ROM to map to the top of 4G address space - and thus the 2nd I/O hole was born. Of course, at the time, nobody in their right mind anticipated the platform to last until gigabytes of RAM in a personal computer would be possible - and once again, the architecture didn't get a complete makover to keep things compatible with existing operating systems.
The 486 and Pentium generations gradually added more 32-bit capable I/O devices (VESA local bus graphics, PCI peripherals, as well as chipset-integrated PCI-like peripherals and new system hardware for exclusive use with 32-bit capable operating systems). With the BIOS ROM at the top of address space a given, all that stuff got mapped to right below it. The architecture wasn't changed, for compatibility ... you know the deal.
As we all know by now, RAM sizes started to grow like mad in the Pentium days, and it was quickly anticipated that 32-bit address space wouldn't last long. Intel developed an "extended" processor mode, PAE, that allowed 36 bit addressing, albeit with a rather ugly paged programming model. Once again, the architecture didn't get changed, all the I/O remained where it always was, and the extra RAM appeared on top of it, between the upper bound of the 2nd I/O window at 4G and the end of 36-bit space at 64G.
AMD then added the 64-bit mode to their processors, with 40-bit physical addressing, and Intel followed (but stayed at 36 bits to stay compatible with their existing PAE chipsets). This is where we are now, and the address map is the same as in PAE mode - only with non-paged, linear addressing capability.