- Apr 27, 2000
To the best of my knowledge, the 14nm process has nothing about it that would preclude Intel from implementing their new IceLake uarch. Transistor-to-transistor latency shouldn't be THAT big of an issue that the minor increase in density moving to 10nm/10nm+ for client CPUs would enable a uarch that would be impossible on 14nm++ (or otherwise). At that point it's just a matter of dealing with the (presumably) higher transistor count you'd need for wider cores and more cache. Since Intel is already pimping 8c/16t CPUs and will push out a 10c/20t CPU on 14nm++, it stands to reason that a 6c/12t IceLake would be possible using the same (or less) die real estate.I wasn't thinking so much about the total die size, but what you can do within a single core. I presume you can have bigger and wider register files, caches, buffers and data paths on a smaller process, which aren't feasible on a larger process due to trade-offs in frequency, latency and power.
I have yet to see any indication that Cascade Lake-AP has AVX enhancements over Skylake-SP. Or really any enhancements, at all . . .