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14nm 6th Time Over: Intel Readies 10-core "Comet Lake" Die to Preempt "Zen 2" AM4

Apr 27, 2000
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I wasn't thinking so much about the total die size, but what you can do within a single core. I presume you can have bigger and wider register files, caches, buffers and data paths on a smaller process, which aren't feasible on a larger process due to trade-offs in frequency, latency and power.
To the best of my knowledge, the 14nm process has nothing about it that would preclude Intel from implementing their new IceLake uarch. Transistor-to-transistor latency shouldn't be THAT big of an issue that the minor increase in density moving to 10nm/10nm+ for client CPUs would enable a uarch that would be impossible on 14nm++ (or otherwise). At that point it's just a matter of dealing with the (presumably) higher transistor count you'd need for wider cores and more cache. Since Intel is already pimping 8c/16t CPUs and will push out a 10c/20t CPU on 14nm++, it stands to reason that a 6c/12t IceLake would be possible using the same (or less) die real estate.

I was thinking about the AVX enhancements in the server parts, yes, as evidence for Intel's AVX focus, which I understand is the major enhancement for Ice Lake, apart from improved iGPU and memory support (ref. Wikipedia and Wikichip).
I have yet to see any indication that Cascade Lake-AP has AVX enhancements over Skylake-SP. Or really any enhancements, at all . . .
 

Vattila

Senior member
Oct 22, 2004
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I have yet to see any indication that Cascade Lake-AP has AVX enhancements over Skylake-SP.
As @LTC8K6 points out, Cascade Lake has the AVX-512 VNNI - AVX-512 Vector Neural Network Instructions. This seems to be a backport from Ice Lake. (Wikichip)

This fact is part of my intuition that Intel's roadmap was mainly focussed on AVX innovations. The higher density and much lower power of the 10nm process would be very good for vector processing. And back when these plans were made, Intel's sole strategy for parallel compute was AVX and Xeon Phi (Knights architecture). I guess Ice Lake has very few microarchitectural innovations. They probably felt so far ahead of AMD that they saw no need to reinvent the core to gain IPC or frequency, and most low-hanging fruit has probably been plucked.
 

Zucker2k

Senior member
Feb 15, 2006
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Intel historically implemented "big" arch changes in the relative safety of testing new process first with a conservative upgrade. Presuming their next arch is something that demands specific area and power improvement in order to function (as an upgrade) at all paints an even more reckless and desperate Intel than I would like to imagine.

It's as if until 14nm they had a nice tick / tock thing going, after which they decided to enter Icarus YOLO mode and reach for the Sun or die trying. I don't buy it.


And an improved architecture would better the 9900K with no need of increased power draw. Unless you think Skylake is the epitome of x86 performance and efficiency, in which case we'll all be rocking iPhone CPUs in a few years time.

This is not about Intel vs. AMD or some other petty forum brawl. This is about Intel essentially recycling their Skylake arch for the past 3 ½ years (and having multiple teams developing better designs during that timeframe). It's Intel vs. Intel if you will.
My reference to the 2950x is simply to highlight what increased power budget can do to single core clock frequency. On your other points, Intel has to work with what they have NOW. They haven't had 10nm for a while and they just can't rollover and die. Depending on what AMD rolls out, Intel may need that 10 Core to stay competitive until 10nm chips arrive.
 

maddie

Platinum Member
Jul 18, 2010
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To the best of my knowledge, the 14nm process has nothing about it that would preclude Intel from implementing their new IceLake uarch. Transistor-to-transistor latency shouldn't be THAT big of an issue that the minor increase in density moving to 10nm/10nm+ for client CPUs would enable a uarch that would be impossible on 14nm++ (or otherwise). At that point it's just a matter of dealing with the (presumably) higher transistor count you'd need for wider cores and more cache. Since Intel is already pimping 8c/16t CPUs and will push out a 10c/20t CPU on 14nm++, it stands to reason that a 6c/12t IceLake would be possible using the same (or less) die real estate.



I have yet to see any indication that Cascade Lake-AP has AVX enhancements over Skylake-SP. Or really any enhancements, at all . . .
Intel claimed a ~2.7X density improvement, hardly a "minor increase in density". A massive increase in transistor budgets would allow all manner of new possibilities.

Its obvious that the fab teams kept expecting and claiming a resolution of the issues "soon". If it worked as planned, they would be gods in the company. The doubters were punished and/or banished. We see this mentality all around us in myriad fields today. Recent core count increases are a belated attempt to rectify their negligence in preparing contingency plans. That is their sin, the arrogance in assuming they would always prevail. "WE ARE INTEL"
 

coercitiv

Platinum Member
Jan 24, 2014
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My reference to the 2950x is simply to highlight what increased power budget can do to single core clock frequency.
This is mainstream, not HEDT. And TDP has nothing to do with single core clock frequency, not on high performance desktop parts anyway.

On your other points, Intel has to work with what they have NOW.
This exactly what we are discussing.
 

IntelUser2000

Elite Member
Oct 14, 2003
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To the best of my knowledge, the 14nm process has nothing about it that would preclude Intel from implementing their new IceLake uarch.
A 14nm "Icelake" will no longer be Icelake. Modern CPUs are bound by power limits. New processes offer lower power, which can be used to increase performance. You can try to extract more performance at same power, but there are limits. Even their 1% increase in power for 1% increase in performance rule still means 1% increase in power!

And you know what? Regarding clocks. I'd prefer Icelake 4.5GHz that performs 10% faster per clock over Coffeelake 5GHz.

Though even a 5% increase in perf/clock will be welcome. We could have seen a new architecture 14nm, but it had to be planned for it.

Unfortunately, they did not plan on 10nm failling this bad.

2016 with Skylake: "Oh we'll get 10nm in 2016"
2017 with Kabylake: "Oh we'll get 10nm in 2017"
2018 with Coffeelake: "We'll definitely get 10nm in 2018"

That's how we end up with a 14nm Skylake in 2019. I refuse to call a 9900K Coffeelake now. 9900K = 8 core Skylake.
 

coercitiv

Platinum Member
Jan 24, 2014
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A 14nm "Icelake" will no longer be Icelake. Modern CPUs are bound by power limits. New processes offer lower power, which can be used to increase performance. You can try to extract more performance at same power, but there are limits. Even their 1% increase in power for 1% increase in performance rule still means 1% increase in power!
True, but the argument @DrMrLordX made was based on the idea of comparing something like 10C Skylake with 8C "Icelake", starting from an 8C Skylake baseline. In this scenario we are already discussing a potential ~25% increase in power (assuming ISO clocks).

Think about it in reverse, if 8C "Icelake" makes little sense over 8C Skylake because of power restrictions, what sense does 10 Skylake make over 8C?!
 

maddie

Platinum Member
Jul 18, 2010
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True, but the argument @DrMrLordX made was based on the idea of comparing something like 10C Skylake with 8C "Icelake", starting from an 8C Skylake baseline. In this scenario we are already discussing a potential ~25% increase in power (assuming ISO clocks).

Think about it in reverse, if 8C "Icelake" makes little sense over 8C Skylake because of power restrictions, what sense does 10 Skylake make over 8C?!
Pure marketing driven as a response to AMD. Intel lately, has obviously abandoned their previous calm advancement of plans.
 

jpiniero

Diamond Member
Oct 1, 2010
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Pure marketing driven as a response to AMD. Intel lately, has obviously abandoned their previous calm advancement of plans.
Well, they have to release something new every year. Rehashing Skylake yet again is the only real option, so they don't have too many ways to offer an improvement. The only other idea I had would be to add HT to all the models, with the i9 model being a top bin like the 8086K. But yes I guess marketing thought 10 cores sounded better.
 

IntelUser2000

Elite Member
Oct 14, 2003
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Think about it in reverse, if 8C "Icelake" makes little sense over 8C Skylake because of power restrictions, what sense does 10 Skylake make over 8C?!
It's true, what you are saying. But I'm not sure if its an advantage going for an 8C Icelake over 10 core Skylake. Perhaps people are willing to accept power increase to get 25% more cores. They are both suboptimal ways to go about it.

We were supposed to have 8 cores with the original Cannonlake, so 10 cores might have been too much even on the 10nm process. 10 core Icelake is pushing it already taking account core wars sorry, competition, and maybe a 10++ Tigerlake would have been needed to get an optimal 10 core going.

Is enough of Intel aware that even the original plans of having 10++ by late 2019 was a very sucky, sucky plan and we are way past that point now? Possibly into hyperspace? I thought Skylake in late 2015 was a disappointment.
 
Mar 10, 2004
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We've still only had 14nm,14nm+ and 14nm++.

We have not yet seen anything beyond ++.

Is there any more room for improvement?

Would there be any point to a 14nm+++ node?
 

jpiniero

Diamond Member
Oct 1, 2010
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We've still only had 14nm,14nm+ and 14nm++.

We have not yet seen anything beyond ++.

Is there any more room for improvement?

Would there be any point to a 14nm+++ node?
They are making further improvements, and Comet Lake will likely have those, but they are getting away from the + branding so maybe they will just call it "14 nm class" like how AT describes it.
 

coercitiv

Platinum Member
Jan 24, 2014
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It's true, what you are saying. But I'm not sure if its an advantage going for an 8C Icelake over 10 core Skylake.
Must resist sarcasm overload. Must keep calm. Oh to hell with it: SINGLE THREAD PERFORMANCE!!! AAAARGH!!! That day @coercitiv 's pressure valves malfunctioned and his tiny avatar head blew up in a small puff of smoke. Decent bloke, he liked reading about CPUs.

PS: they would both be limited by mainstream TDP even if increased towards 120-140W, but whatever ICL brings in terms of IPC would translate into ST performance as well.
 

Zucker2k

Senior member
Feb 15, 2006
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True, but the argument @DrMrLordX made was based on the idea of comparing something like 10C Skylake with 8C "Icelake", starting from an 8C Skylake baseline. In this scenario we are already discussing a potential ~25% increase in power (assuming ISO clocks).

Think about it in reverse, if 8C "Icelake" makes little sense over 8C Skylake because of power restrictions, what sense does 10 Skylake make over 8C?!
Take a 9900k's 95Watts. Now, let's assume the 10 Core has a lineal 25% increase in power budget = 118W. What do you think this 10 Core is going to do running 16 threads like the 9900k with 25% more power at it's disposal? They can afford to go aggressive on the per core power profiles and outperform the 9900k in every scenario, single core included (why not?)
 
Apr 27, 2000
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A 14nm "Icelake" will no longer be Icelake. Modern CPUs are bound by power limits. New processes offer lower power, which can be used to increase performance. You can try to extract more performance at same power, but there are limits.
I think others have already addressed your point quite well. All I can add is that it seems like this discussion already played out in private during several meetings at Intel. We know which path Intel chose.

Intel claimed a ~2.7X density improvement, hardly a "minor increase in density". A massive increase in transistor budgets would allow all manner of new possibilities.

Its obvious that the fab teams kept expecting and claiming a resolution of the issues "soon". If it worked as planned, they would be gods in the company. The doubters were punished and/or banished. We see this mentality all around us in myriad fields today. Recent core count increases are a belated attempt to rectify their negligence in preparing contingency plans. That is their sin, the arrogance in assuming they would always prevail. "WE ARE INTEL"

2.7X seems bogus at this point. Even the i3-8121U with it's dize size of 70 square millimeters isn't THAT much smaller than something like the i3-8145U which is . . .123 square millimeters? Granted that doesn't take transistor count into effect (Cannonlake has AVX512 in there, I think, and the 8121U does have an iGPU in there even if it doesn't work). But that ain't 2.7X. Maybe for SRAM.

Anyway I don't know that 8c IceLake would be possible in the same die area as 8c or 10c CoffeeLake, but 6c IceLake should have been possible. At the time the decision was made not to backport IceLake, Intel likely hadn't even released CoffeeLake at all.

AVX-512 VNNI - AVX-512 Vector Neural Network Instructions

Cascade Lake added that, whatever it is.

https://en.wikipedia.org/wiki/AVX-512#New_instructions_in_AVX-512_VNNI
Okay, I didn't notice that. That'll help in AI/deep learning algorithms, but elsewhere? Ehhhhh.
 
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jpiniero

Diamond Member
Oct 1, 2010
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2.7X seems bogus at this point. Even the i3-8121U with it's dize size of 70 square millimeters isn't THAT much smaller than something like the i3-8145U which is . . .123 square millimeters?
Cannonlake's 2+2 die has 40 EU and not 24 like the GT2 of Skylake and friends.
 
Apr 27, 2000
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Cannonlake's 2+2 die has 40 EU and not 24 like the GT2 of Skylake and friends.
Do we have official transistor counts between the dice? That might shed more light on the situation.
 

IntelUser2000

Elite Member
Oct 14, 2003
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We know which path Intel chose.
Intel might not have had a choice, if the rumors for Comet Lake U chips are true. If they can't make those, what chance they'll have at a near-5GHz 8 core?

But that ain't 2.7X. Maybe for SRAM.
It's not even for SRAM. It's for Atom chips. I bet Core chips were unaffected by "12nm" changes to their 10nm.

I don't know what they were thinking. Sacrifice bread-and-butter Core chips to get Atoms into 5 million phones for Asus?

Anyway I don't know that 8c IceLake would be possible in the same die area as 8c or 10c CoffeeLake, but 6c IceLake should have been possible.
This depends on how extensive the core changes are. Nehalem was like 45% larger than Penryn, and Sandy Bridge was 40% larger than Clarkdale. Haswell might have been in the 20-30% range over Ivy Bridge.

Even with 50% larger cores though, the die of a 10 core 10nm Icelake should be smaller than 6 core Skylake.
 

The Stilt

Golden Member
Dec 5, 2015
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AMD has been tweaking the power management on Pinnacle Ridge CPUs after the launch.
Certain SMU FW versions released soon after the launch went a bit too far, and the deployment resulted in slight reduction in performance as well.
Several versions have been released since and more fine tuning seem to have taken place. AMD has also completely revamped the XFR Enhancement / Precision Boost Override -feature after the launch.
In its current form it no longer allows individual control of the limiters, simply on / off toggle.

Comparing the different power figures is utterly futile, since there are way too many variables.
I suggest that you pick five reviews from reputable sources and discard the lowest and the highest recorded power figures. Then calculate the average of the remaining three.
Obviously there will still be specimens drawing somewhat more and less power than that, but the figure you got is more than close enough for this kind of purposes.
 

jpiniero

Diamond Member
Oct 1, 2010
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Do we have official transistor counts between the dice? That might shed more light on the situation.
Intel doesn't disclose transisitor counts. My guess is that it would be at least 140 mm2 if it was on 14 nm, and probably a bit more.
 
Nov 6, 2018
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Rumour: Ryzen 3000/x570 to have 16c/32t
Are you talking about this one?


It's still just a rumour but I wouldn't be that surprised at all if Ryzen 3000 (AM4) would be launching with two Rome chiplets (72 mm², 7nm) and a smaller IO die (about 105 mm², 14nm). The rumour suggests that Ryzen 3000 (AM4) would initially only be 12C/16C so lower end models might still be 12nm for a while.

At 14:44 he talks about communication challenges between CCX's which could also point to a chiplet design. At this point I find 16C monolithic die highly unlikely but obviously, I could also be wrong. In my opinion, 12C (or even only 8C) with 3 CCX's would have been a better bet for a monolithic die.

I'm not taking sides here but this is still one possibility. I'm not sure if I really hoped for this but all things considered, it wouldn't really be that unexpected. We'll see. I'll just leave this there, I'm not in the mood to contemplate this any more.

Addition: He says (in the video) that Ryzen 3000 (AM4) would (at first) be minimum of 12 cores (16 cores max) and not all current AM4 motherboards might be able to handle the power requirements (there is a debate between AMD and MB vendors whatever AMD is pushing the core count too hard). There should still be significant IPC and clock speed improvements but the problem might be that AMD has taken too ambitious steps with core counts on AM4 platform regarding the power usage and compatibility is at risk. HEDT would still have 4 MC vs. 2 MC (on AM4). I don't know what to think about this anymore but if his source is reliable then AMD is really pushing it (possibly with their chiplet design). Still it's just a rumour but we'll see.

Addition 2: He also says that both Ryzen 3000 and (likely) Navi (at 15:08 on the video) would launch at Computex 2019.
 
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Oct 10, 1999
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Are you talking about this one?


It's still just a rumour but I wouldn't be that surpriced at all if Ryzen 3000 (AM4) would be launching with two Rome chiplets (72 mm², 7nm) and a smaller IO die (about 105 mm², 14nm). The rumour suggests that Ryzen 3000 (AM4) would initially only be 12C/16C so lower end models might still be 12nm for a while.

At 14:44 he talks about communication challenges between CCX's which could also point to chiplet design. At this point I find 16C monolithic die highly unlikely but obviously, I could also be wrong. In my opinion, 12C (or even only 8C) with 3 CCX's would have been a better bet for a monolithic die.

I'm not taking sides here but this is still one possibility. I'm not sure if I really hoped for this but all things considered, it wouldn't really be that unexpected. We'll see. I'll just leave this there, I'm not in the mood to contemplate this any more.
Yup.
 

dlerious

Senior member
Mar 4, 2004
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Are you talking about this one?


It's still just a rumour but I wouldn't be that surpriced at all if Ryzen 3000 (AM4) would be launching with two Rome chiplets (72 mm², 7nm) and a smaller IO die (about 105 mm², 14nm). The rumour suggests that Ryzen 3000 (AM4) would initially only be 12C/16C so lower end models might still be 12nm for a while.

At 14:44 he talks about communication challenges between CCX's which could also point to a chiplet design. At this point I find 16C monolithic die highly unlikely but obviously, I could also be wrong. In my opinion, 12C (or even only 8C) with 3 CCX's would have been a better bet for a monolithic die.

I'm not taking sides here but this is still one possibility. I'm not sure if I really hoped for this but all things considered, it wouldn't really be that unexpected. We'll see. I'll just leave this there, I'm not in the mood to contemplate this any more.
I don't see them competing with their HEDT chips. They've also promised support for AM4 til 2020.
 

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