There should be plenty of motherboards equipped with beefy VRMs
Let's hope so! Gigabyte is preparing this . . . lovely board:
https://www.techpowerup.com/229076/gigabyte-ax370-gaming-k3-socket-am4-motherboard-pcb-pictured
4+3 phase VRM? Is this a cheap-arse config intended for Bristol Ridge? Eww?
Asus do better! We want 8+2 phase or better stat!
I'll give you a hint: 40% IPC increase over Excavator matches almost exactly the IPC of Sandy / Ivy Bridge. Not Broadwell-E's, which appears to be the case.
I remember going around and around about this with some people earlier in the Zen rumour cycle. See below.
You're attacking him like rabid dogs. It's not like he's going full CENSORED and refusing to admit the possibility that he was wrong even when evidence goes against it.
If anyone can bring it like . . . that guy . . . they'll win even when they're wrong! That is why he is Internet Strong Man.
Oh hell no. Don't even mention that name, who knows, he may be summoned in some way or form.
!!!!!!
!!!!
!!
omg hide
this.
people be crazy in this thread for absolutely no reason. On both sides.
I may be crazy, but I try to be nice about it.
Whats happening with Zen is the opposite of whats happening with Zen.
So you always expected Zen to have the same/higher IPC than BDe?
I won't speak for anyone but myself here, but after seeing Dresdenboy's diagrams about estimated core architecture for Summit Ridge, I realized that there was no way in hell it was going to have the same
throughput as Ivy or Sandy, and that it would be possibly better than Haswell. Unless someone from AMD really screwed up the design. That plus what we were told about the changes in the cache hierarchy should have resulted in better-than-Ivy performance, though.
The only statement we had from AMD for a long time was "40% better IPC than XV" which is tricky since XV is a CMT design. Lots of people were looking at XV's horrid ST performance and making estimates on that basis. I figured that AMD would be criminally insane to make such a statement in reference to XV's ST performance. So I went back to the old-school definition of IPC, and assumed it would track linearly on a core-per-core basis as in the K10/Core2 days. So 40% higher IPC would mean 40% higher throughput, right?
It turned out that I was misinterpreting AMD's statement, and they did mean ST IPC.
My estimates were largely based around an admittedly-limited inspection of XV's MT performance in Cinebench R10 - the last Cinebench version where AMD processors seemed to hold up okay on a per-thread basis (they suffer in the later iterations). In CB R10, a 3.4 GHz Carrizo can almost hang in there with a 3.4 GHz i3 in the MT score department; that is, on a per-thread basis, XV is doin alright. I figured if Summit Ridge would give us 40% better than
that, there's no way it was going to be trading blows with Sandy Bridge.
Turns out that by being wrong, I was sort of right.
It all comes back to core width, though. Summit Ridge is wide, with a lot more dedicated to fp performance than you see in Con modules.
From the moment we knew the uarch it was clear that they were targeting intel s latest iterations, indeed no one in his right mind would imagine that they would compete adequatly with SB/IB perfs level.
See above. If you only take XV's ST performance and then boost that by 40% and then add in ~%30 for SMT, you get something in the Sandy/Ivy range. Which would have sucked ass. When AMD came out and clarified their statements and confirmed that it was +40% over XV's ST performance, it looked like that might be correct! Good thing so many people were wrong!
We still don't know a lot about Summit Ridge's ST performance. Summit Ridge may just have amazing SMT implementation, or . . . something. I dunno really.