First ES? Doubt anyone has a clue.What was the clock of first 14nm INTEL batches?
Do i really need to remind you they never demonstrated chip's power consumption, not to mention they have used a very light load for such illustration? Not to mention, what makes you think it was actually overvolted? Oh, and finally, name a single process that have improved in power consumption with a simple maturity nearly as severely as you suggest Zen shall. Intel failed to do so with actual node change, for pete's sake!AMD is going desktop first and demonstrated an overvolted 3.4GHz chip to draw less than 95W...
The "per core" part i don't remember. For all i care, they have compared a single core with 2 threads and a module power consumption wise. Here, a twist, and your forecast looks out of touch with reality.If we stick with AMD promise of same energy/clock per core as XV
I have no clue what FO4 either Zen or BW/SKL have. For all i care, it is irrelevant.Remember that Zen has lower FO4 than BW/SKL... Otherwise they couldn't manage to have higher clocks and lower power on an inferior process, with an overvolted ES...
Whoops, sorry for not following that clearly. I don't know, I think they would have chosen 14nm HP from the beginning if that were the case. Zen doesn't look to be due for an update until Zen+ on 7nm in 2H '18.im not talking about Zen, originally we where talking about a Zen follow on and what process it would use. Which lead to the does GF actually run the 14nm process IBM created, to which i answered with it looks like it because the IBM chip architect calls the process GF 14nm HP.
...instead of refreshing Zen on 14nm in 1H '18 I just see a 7nm release in Q4 '18 or Q1 '19 when 7nm @ GloFo is ready
They did bulldozer to piledriver in 12 months. I dont see why Zen would be any different. steamroller and excavator aren't good examples because they had other issues at the time like inventory management. There is like lots of low hanging fruit they can hit (much like piledriver) without making massive uarch changes.Whoops, sorry for not following that clearly. I don't know, I think they would have chosen 14nm HP from the beginning if that were the case. Zen doesn't look to be due for an update until Zen+ on 7nm in 2H '18.
Steamroller > Excavator (Carrizo) took almost a year and a half...instead of refreshing Zen on 14nm in 1H '18 I just see a 7nm release in Q4 '18 or Q1 '19 when 7nm @ GloFo is ready
Well the question is if this GF 14 HP will materialize at all. Looking at GF prior execution one can cast some doubt on it? Where is eg soi or some cheaper alternatives to finfet seronx was brabling about. Its gone i asume.
One can understand gf needs something higher perf than what goes into galaxy s9 but what is your take on what will happen?
We saw piledriver a year after bd with some easy gains. But zen looks far more balanced out the gate.
The quesion is. Will we see zen+ before 7nm? If yes. One should asume 14 HP is ready as amd hardly have ressources to just make a new zen+ on the same process they have now. Or what?
Do i really need to remind you they never demonstrated chip's power consumption, not to mention they have used a very light load for such illustration? Not to mention, what makes you think it was actually overvolted? Oh, and finally, name a single process that have improved in power consumption with a simple maturity nearly as severely as you suggest Zen shall. Intel failed to do so with actual node change, for pete's sake!
The "per core" part i don't remember. For all i care, they have compared a single core with 2 threads and a module power consumption wise. Here, a twist, and your forecast looks out of touch with reality.
I have no clue what FO4 either Zen or BW/SKL have. For all i care, it is irrelevant.
Hmm. I dont think its that simple and that there is conflicting information:They did bulldozer to piledriver in 12 months. I dont see why Zen would be any different. steamroller and excavator aren't good examples because they had other issues at the time like inventory management. There is like lots of low hanging fruit they can hit (much like piledriver) without making massive uarch changes.
Now the question we need to answer is that 12 months extra enough time to have based the design on 14nm HP.
The Power9 design was done on IBM 14nm. That is completely different to GF 14nm ( Samsung 14nm ). Given the deal with IBM mandate the continue production my guess is that it will be on different team, and on low priorities.
The 22FDX , FD-SOI is actually right on track . Not sure if AMD will use it though.
Hmm. I dont think its that simple and that there is conflicting information:
Where should the low hanging fruit be looking at the zen results?
For bd they eg implemented a clock mesh technology. And could improve freq to where it was intended.
And loking at how late gf 14nm was implemented i seriously have doubt they could ready in a year. As say work on improving yield on existing process.
What i think looking at the results is that amd should have plenty access to funding for new activities be it arch or process work. Unlike the last 10 years they are in a good position. With a ceo really fit for where the company is going and a good roadmap.
It looks like a bit of mess to me. A lot of nodes and few ressources. It doesnt add up.
1. Power 9 14nm hp process
2. 22FDX
3. FD-soi
4. 14 lpp
5. 7nm
Yep they skipped 10nm. No sh!t. That was a tough choice. Lol.
And who is the buyer besides amd? How many power9 is sold.
But yeaa if ibm can fund the 14HP nearly 100% there is a bit of sense but...
1. You do not account for PSU efficiency not being a constant.Not at new horizont event, but at the twin event on december 8, for the press, under NDA, they showed the power consumtion and was about 94W difference between idle and full load (blender). Subtract PSU and VRM efficiency and you have under 80W. The video can be found in youtube and the link was given somewhere here on anand and all other forums... I don't know how come you have not seen it... Or maybe you are ignoring it...
Footnote relates to the asterisk on "work per cycle". Energy per cycle does not have a single foot note relating to what it compares. So, my theory about it being module vs SMT core stands. What now? Oh, and btw, you may just right, and it does compare core for core. But then don't you find it funny for your claim that power consumption per cycle did not drop one iota despite such a ridiculous node shrink?Here: http://www.anandtech.com/show/10591...t-2-extracting-instructionlevel-parallelism/8 5th slide. Take a look on the small foot note... It says explicitly 1 core vs 1 core, zen vs excavator... Since 1 isolated XV core does not exist, this means 2 zen core draw same power of an XV module. It's all simple like that. But somehow you ignored it...
1. BWE was running at higher clock, actually.How can zen draw less power than BWE at an higher clock with an inferior process? Magic? No! Lower FO4.
1. You do not account for PSU efficiency not being a constant.
2. My point about load being light stands, though i do expect that in Prime95, Zeppelin will consume significantly less than BWE.
Footnote relates to the asterisk on "work per cycle". Energy per cycle does not have a single foot note relating to what it compares. So, my theory about it being module vs SMT core stands. What now? Oh, and btw, you may just right, and it does compare core for core. But then don't you find it funny for your claim that power consumption per cycle did not drop one iota despite such a ridiculous node shrink?
1. BWE was running at higher clock, actually.
2. BWE has a proper separate chipset and way larger uncore with it, Zeppelin from all we know... not quite.
See, and i did not even need to bring up EE for nothing.
Well if 14HP is running as you outline surely it makes sense for a q1 18 slightly facelifted zen. I wouldnt bet on excess of 5%.Exactly the same kind of stuff the did with PD, improve prefetch and predict improve handling of edge case ops, further tuning of SMT weights/priorities, increases to queue sizes, further improvement in memory disambiguation etc etc. All of these features you don't just do once you continually iterate on them. But Zen is the first in the line and you are never going to get everything perfect first time around.
If they move to HP there is likely to be more clocking head room, Power9 is shipping H2 17 so Q1 18 14HP should be well on its way. So you could end up with that 5-10 points of IPC (depending on workload) and a few hunder extra Mhz on base and or turbo.
You do not account for PSU efficiency improving with load on most of decent PSUs. Using the OP article, we learn that with VRMs 3.3Ghz Zeppelin consumes about 94W on light load. Even assuming it is one of the earlier samples that it is not, there is a long road to your claim on clocks to power consumption.Constant or variable, they are max 90% both. 80W is an upper limit.
Sure, quote me on the sentence you attribute to me.Let's decide.
Since they were measuring system performance, it actually plays in favor of BWE power consumption wise. I'll let you figure out how. But anyways, there is little to discuss now, because while it is entirely possible Zeppelin will get a 20% clock uplift over what was shown in Canard article, it most certainly won't happen in the same power envelope.I am not sure that BWE has on die USB, sata and GB ethernet...
EDIT. Moreover Zen is a SoC, BWE, not. It has PCIex, MC, USB, Sata, GB ethernet... I am not sure that BWE has on die USB, sata and GB ethernet...
What do you mean? Why would AMD add that to their processor, increasing thermal power and increase die size?
What do you mean? Why would AMD add that to their processor, increasing thermal power and increase die size?
You do not account for PSU efficiency improving with load on most of decent PSUs. Using the OP article, we learn that with VRMs 3.3Ghz Zeppelin consumes about 94W on light load. Even assuming it is one of the earlier samples that it is not, there is a long road to your claim on clocks to power consumption.
Sure, quote me on the sentence you attribute to me.
Since they were measuring system performance, it actually plays in favor of BWE power consumption wise. I'll let you figure out how. But anyways, there is little to discuss now, because while it is entirely possible Zeppelin will get a 20% clock uplift over what was shown in Canard article, it most certainly won't happen in the same power envelope.
As explained AM4 CPUs are true SoCs. On inexpensive motherborads or small form factor or in notebook/tablets, all that integrated in the CPU is sufficient, so no external chips are needed. Only premium motherboards need external chipset.What do you mean? Why would AMD add that to their processor, increasing thermal power and increase die size?
When was the last time Intel had to lower prices in the enthusiast / desktop space due to competition? I really hope these early benches have merit. This is an encouraging sign whether you want to buy AMD or Intel for your next build.
When was the last time Intel had to lower prices in the enthusiast / desktop space due to competition? I really hope these early benches have merit. This is an encouraging sign whether you want to buy AMD or Intel for your next build.
I'd love to see a 2C/4T or 3C/6T Zen core APU with good clocks, give it 12-14CU's/768-896SP's (Polaris) and some fast DDR4.
Yep. It seems so.Phenom II?