Question Zen 6 Speculation Thread

[LightningZ71]

The absolute best that anyone could have hoped for was a custom chop of an existing product, like a gorgon point 2 with no NPU and half the I/O removed, but to make it actually worth it, they would need a new floorplan, and AMD isn't about to bother with that.

And, lets not kid ourselves, there is ALWAYS a dollar amount that gets things done, but that amount is WAY over and above what they could afford to pay and still break even with multiples of their projected volume.

If you want something, you'll have to make it make sense starting with an existing SKU and work from there.

 

[511]

Money's not the problem (Valve's rich). It's the units total that gatekeep stuff.

nowhere near MSFT

Xbox gets one too. But not Valve.

Xbox get that due to their deep pockets

 

[Win2012R2]

this stuff isn't cheap AT ALL...

Valve got lots of money, it's them who is cheap here.

At this rate Deck 2 will be Intel+nGreedia

 

[gdansk]

At this rate Deck 2 will be Intel+nGreedia

And who would complain about that? Why be mad about getting a system that can actually play games the way gamers demand?
If AMD doesn't want to undercut them there's nothing lost for us. You just consume some Intel or Qualcomm instead and be happy.

 

[Tachyonism]

But they captured it accidentally without designing a single SoC for handhelds. A few special SKUs here and there and the consumers buy it up.

It was by sheer luck. And there were no competitors at the time.

And who would complain about that?

Probably Gabe. Expensive part and ass driver on Linux.

 

[lamedude]

Nvidia on my SteamOS?

 

[gdansk]

Probably Gabe. Expensive part and ass driver on Linux

I shed zero tears over a billionaire wanting custom silicon for free.
The gamers will still have a bunch of options outside of whatever Valve ends up using. The market is full of chips that work OK in handhelds.

 

[adroc_thurston]

Xbox get that due to their deep pockets

They have volumes.
Vulva, not.

 

[Win2012R2]

They have volumes.

How many "Xbox" PCs do you think they'll sell to console crowd in US with price being above $1000?

Right now (after 5 years) they've got sold 35 mln current gen Xboxes, of which Series X is no more than 1/3 of that, so just over 10 mln. That's comparable with Steam Deck sales, and new stuff will be a lot more expensive with no exclusives.

It's gonna bomb, hard - I actually think they'll can it and spin off software game division as a separate company.

 

[gdansk]

How many "Xbox" PCs do you think they'll sell to console crowd in US with price being above $1000?

Well not a lot. Even if Xbox made the best hardware and ran Windows games it still won't sell because it's a dead brand.
But... probably still more than SteamDeck. In every case Zen 6 isn't that important or even really a selling point.

 

[Tachyonism]

The gamers will still have a bunch of options outside of whatever Valve ends up using.

Yeah but we are specifically talking about Steam Deck 2.

The market is full of chips that work OK in handhelds.

What's there beside Intel and Qualcomm.

 

[Win2012R2]

Well not a lot

Their current sales are down to near zero - apparently 1.28 mln of S+X in 2025, and they had price increases near end of year for X.

Microsoft will weasel out of their contact - no way they'll be able to guarantee comparable sales to Xbox, most of which was S anyway.

With Sony's apparent move back to real exclusives PS5/6 is the only console game in town (not counting portable Switch here).

 

[OneEng2]

No, that is desd.
AVX10 is 512b only.

Someone please provide proof that AVX10 will be implemented in Intel processors using ONLY 512b wide path execution. The SPEC CLEARLY indicates the purpose of the extension is to allow multiple bit width implementations for a single instruction set.

Yes, I'm aware (now) but how many developers have actually utilized that in their code?

I think it is more important that compilers support it. That's where the support actually comes from. Of course, new versions of apps must be made with the new compiler, but this is getting easier and easier as time goes by IMO.

 

[adroc_thurston]

How many "Xbox" PCs do you think they'll sell to console crowd in US with price being above $1000?

Plenty.

Someone please provide proof that AVX10 will be implemented in Intel processors using ONLY 512b wide path execution. The SPEC CLEARLY indicates the purpose of the extension is to allow multiple bit width implementations for a single instruction set

If you have methylene blindness not even I can fix it.

 

[Win2012R2]

Someone please provide proof that AVX10 will be implemented in Intel processors using ONLY 512b wide path execution.

512b will be register size, execution will be like Zen4 on platforms that don't need full speed.

 

[gdansk]

What's there beside Intel and Qualcomm.

Every highend laptop and flagship phone SoC has hardware more capable than a $600 handheld can reasonably be equipped with. They are unfortunately not as GPU focused as gamers want except maybe PTL

 

[Win2012R2]

Plenty.

How many units over say 5 year period?

 

[OneEng2]

AVX 10.2 states that it supports 128, 256 and 512b paths but that 512b is manditory while in 10.1 it was optional.

Not sure how this will be utilized, but it seems hard to believe that Intel e cores will have 512b paths in them. If someone has a link to some information showing otherwise, I would love to see it.

 

[inquiss]

Just re

AVX 10.2 states that it supports 128, 256 and 512b paths but that 512b is manditory while in 10.1 it was optional.

Not sure how this will be utilized, but it seems hard to believe that Intel e cores will have 512b paths in them. If someone has a link to some information showing otherwise, I would love to see it.

Maybe read the last two pages of this thread and it's like, really clear. It's literally explained in this thread how it works. Read the thread, I'd suggest, for more knowledge and answers.

 

[Joe NYC]

Someone please provide proof that AVX10 will be implemented in Intel processors using ONLY 512b wide path execution. The SPEC CLEARLY indicates the purpose of the extension is to allow multiple bit width implementations for a single instruction set.

I think you are confusing 2 things:
- instruction support
- implementation of those instructions

Mandate that AVX 10.2 supports 512-bit wide means that it has to support 512-bit wide instructions.
Which implies that all: 128, 256 and 512bit wide instructions are supported.

As far as implementation, it is up to the CPU makers. Zen 5 desktop and server is full 512 wide while Zen 5 mobile and Zen 4 were 256 bit wide.

 

[Tuna-Fish]

If AMD want to capture the handheld market, they need a custom line for these kinds of products. But it's understandable that it's a too risky bet for the company.

It's not that the risk is high, but the TAM is seen as too small. Maybe if xbox/sony handhelds sell really well, there is more interest in the segment?

 

[poke01]

It's not that the risk is high, but the TAM is seen as too small. Maybe if xbox/sony handhelds sell really well, there is more interest in the segment?

Sonys will sell a lot. I.e more than 20 million

 

[OneEng2]

512b will be register size, execution will be like Zen4 on platforms that don't need full speed.

This is useful (unlike quite a few other replies above).

I think you are confusing 2 things:
- instruction support
- implementation of those instructions

Mandate that AVX 10.2 supports 512-bit wide means that it has to support 512-bit wide instructions.
Which implies that all: 128, 256 and 512bit wide instructions are supported.

As far as implementation, it is up to the CPU makers. Zen 5 desktop and server is full 512 wide while Zen 5 mobile and Zen 4 were 256 bit wide.

I believe I have the confusion figured out. Both of these replies got me researching in the right direction.

So here is how it appears to work.

First, AVX10.2 isn't the same as AVX512. In other words, a compiler that ONLY supported AVX10.2 would run in fall back mode on Zen 5 NOT AVX512.

Second, AVX10.2 requires 32 x 512b registers period.

Third, execution path is determined by the hardware support, but utilizes the same compiled code. Execution path can be 128b, 256b, or 512b.

Fourth, there does appear to be additional instructions that do new things above and beyond AVX512 in AVX10.2, but not that much. Mostly, this is exactly what it appears to be. It's a way for Intel to create an instruction set that works across multiple core types to avoid OS scheduling problems .... or to make these operations even possible on a hybrid architecture like ARL. I am not sure if AMD will ever adopt this or not as I am not certain it benefits them AT THIS TIME. Reguardless, AVX512 will continue to be supported especially in DC where it is of the most use.

That's how I have it figured. Now, thanks to those that actually helped.

 

[Covfefe]

It's a way for Intel to create an instruction set that works across multiple core types to avoid OS scheduling problems .... or to make these operations even possible on a hybrid architecture like ARL.

Your understanding here is still incorrect. Hybrid architectures aren't any easier with AVX10 than AVX512.

 

[DrMrLordX]

Well compiler can use it for you like here https://godbolt.org/z/fT1WYfKvz (it's trivial example, but here we are summing 72 floats, there are 16 floats in 512b reg, so it compiles down to 4 512b ops and one 256b op (ymm are 256b regs, zmm are 512b ones).

So knowing compiler can use them for you and/or you can explicitly use them (for example for tail handling, small transpose or gemm kernels etc) it's really hard to give you more detailed answer than: "For sure".

Okay, thanks for presenting at least one example. My own experience with anything beyond AVX2 is pretty limited (since I was on a 3900X for so long), but I do remember ycruncher splitting their executable into a number of different executables targeting different platforms based at least in part on what ISA extensions were supported by the target hardware.

Regardless I don't recall there being a rash of software from (for example) the Rocket Lake or Raphael generation onward utilizing AVX-512 exclusively for all vector lengths. Probably because there's still so much hardware out there that does not support AVX-512 at all, including multiple Intel CPUs released after Rocket Lake.

Eventually it will make sense to target AVX-512 or AVX10 once enough recent generations of consumer hardware support one of those standards.

Your understanding here is still incorrect. Hybrid architectures aren't any easier with AVX10 than AVX512.

Could you elaborate on that?