Question Zen 6 Speculation Thread

[511]

They did!
But a lot of times, you gotta compromise.

Well it's kind of needed cause there are absolutely some stuff that can make use of extra GPR and the new instructions

 

[adroc_thurston]

Well it's kind of needed cause there are absolutely some stuff that can make use of extra GPR and the new instructions

Not the problem.

 

[511]

Not the problem.

Than what's the problem ?

 

[adroc_thurston]

Than what's the problem ?

It's not a clean ISA break like aa64 was.
A stupid half-measure no one really asked for.

 

[511]

It's not a clean ISA break like aa64 was.
A stupid half-measure no one really asked for.

X86_64 sells in the name of compatibility and they probably decided Compatibility is more important for them.

 

[adroc_thurston]

X86_64 sells in the name of compatibility and they probably decided Compatibility is more important for them.

You're not forced to remove amd64! APX is already incompatible anyway from compiler POV.
ffs stop with this stupid garbage. aa32 did not die to aa64.

 

[Nothingness]

Well this is primarily down to Atom guys being really really annoying about it.

IIRC during that period Intel castrated some Core CPU with AVX2 removed.

 

[511]

You're not forced to remove amd64! APX is already incompatible anyway from compiler POV.
ffs stop with this stupid garbage. aa32 did not die to aa64.

APX is a ABI Extension not a clean break like AA64 was over AA32

 

[adroc_thurston]

IIRC during that period Intel castrated some Core CPU with AVX2 removed.

AVX512 but yes.

APX is a ABI Extension not a clean break like AA64 was over AA32

THAT.
IS. THE.
P R O B L E M.
32 arch GPRs and a new prefix already smash compiler assumptions so there was no reason to not do a clean ISA break with a separate exec mode. Alas, Intel is a thing.

 

[511]

THAT.
IS. THE.
P R O B L E M.
32 arch GPRs and a new prefix already smash compiler assumptions so there was no reason to not do a clean ISA break with a separate exec mode. Alas, Intel is a thing.

AMD did the same thing with AMD64 16 GPR

 

[adroc_thurston]

AMD did the same thing with AMD64 16 GPR

Yes and brought a bunch of issues down the line.
Again, aa64 did it well. They copied the whatever parts of aa64 and not the good stuff.

 

[CouncilorIrissa]

AVX512 but yes.

Haswell/Skylake Pentiums lacked AVX2 though.

 

[adroc_thurston]

Haswell/Skylake Pentiums lacked AVX2 though.

Skylake is almost 11 years old, though.
That's ancient history.

 

[LightningZ71]

AVX-512 was supposed to be mainstreamed but ala 10nm happened.

Cough cough Rocket lake cough cough

 

[regen1]

Haswell/Skylake Pentiums lacked AVX2 though.

Yeah, wasn't until Tiger Lake on notebooks and Alder Lake on desktop that 'Pentium' and 'Celeron' branded big "Core" SKUs got up to AVX2.
Technically Rocket Lake didn't have such segmentation but it also didn't have low end SKUs (Pentium, Celeron).

 

[MadRat]

Now that news broke that Sam Altman may have manipulating the DRAM market broke, how might this impact predictions?

 

[adroc_thurston]

Now that news broke that Sam Altman may have manipulating the DRAM market broke, how might this impact predictions?

DRAM prices are 50% up next Q.

 

[blackangus]

Now that news broke that Sam Altman may have manipulating the DRAM market broke, how might this impact predictions?

Is there any talk of any action around what he did?

 

[techjunkie123]

https://www.techspot.com/news/111906-amd-buy-intel-completing-strangest-reversal-chip-history.html

Had me for a minute ngl.

 

[MadRat]

Is there any talk of any action around what he did?

I was more concerned about its impact to Zen 6 speculation. People were accepting low RAM sizes for the average purchase. OpenAI is a dead man walking after the future SaaS news a little while back. One AI is about to win a huge chunk of the market and it is not his.

 

[Nothingness]

AVX512 but yes.

This Coffee Lake CPU from 2020 doesn't have AVX2:

Intel® Celeron® Processor G4950 (2M Cache, 3.30 GHz) - Product Specifications | Intel

Intel® Celeron® Processor G4950 (2M Cache, 3.30 GHz) quick reference with specifications, features, and technologies.

www.intel.com

 

[511]

This Coffee Lake CPU from 2020 doesn't have AVX2:

Intel® Celeron® Processor G4950 (2M Cache, 3.30 GHz) - Product Specifications | Intel

Intel® Celeron® Processor G4950 (2M Cache, 3.30 GHz) quick reference with specifications, features, and technologies.

www.intel.com

isn't this atom?

 

[Nothingness]

isn't this atom?

It clearly states:

Code Name Products formerly Coffee Lake

 

[511]

It clearly states:

Arrow Lake U exists so i can't take this seriously but based on stepping looks like it's a stepping without AVX2 at all

 

[OneEng2]

Do you need AVX-512 for that?

Edit: let me rephrase, do people who buy client CPUs ever need the performance that AVX-512 provides for JSON parsing e.g simdjson?

Arguing that people don't need faster and more efficient computing is kinda silly don't you think? This isn't like the more cores argument since many high performance required applications and average applications use AVX 512. The disadvantage is only in transistor count in the cpu cores.

Why would anyone bother using AVX-512 when many CPUs don’t support it at all?


This, alongside Intel’s initial suboptimal implementations, is the reason why AVX-512 has been so slow to catch on.

I don't think applications are going to STOP using it. If anything, it will work with AVX 10. Intel started the AVX512 instruction set direction, lots of applications have adopted it.

Additionally, AMD's "Server First" approach to design means that where the instructions are MOST beneficial, they will exist. Desktop and Laptop will get it trickle down from there.

Pardon my ignorance but in the future, won't software developers be targeting something like AVX10 or whatever anyway?

Yes, but it is compatible with AVX512. It simply expanded the instructions to be many different bits wide so that the Intel little cores can still execute the instructions without the larger transistor budget. Still, the BEST way to execute AVX 10 is by supporting a 512bit wide AVX instruction and data path.

https://www.techspot.com/news/111906-amd-buy-intel-completing-strangest-reversal-chip-history.html

Had me for a minute ngl.

LOL. It came up in my news feed today as well. Had me for a moment, then reality took over 🙂