Question Zen 6 Speculation Thread

[adroc_thurston]

I imagine that starting with Zen 6 AMD will also be forced to part large cores with a lot of compact cores to be able to keep the competition

Nope, dense in client is for poverty mobile parts.
The others can afford real cores.

 

[Schmide]

Why should they? If you're tossing out 16 and 32 bit encodings that frees up a lot of prefixes. Why wouldn't you want to use them for all the crap using those EREX or whatever the heck ridiculous 8 and 10 byte instructions some of the 64 bit stuff is saddled with?

The CPU could still ALSO handle the current 64 bit encodings (to avoid needing a translator for those) but code using the new encodings would be smaller and make more efficient use of L1I and L2 cache.

That's where I get the small single digit boost - better use of icache. Not worth all the hassle, but you would get SOMETHING out of it if you went through all that.

I think saying "a lot" is a bit more than would actually be affected.

16 REX prefixes that were repurposed from the inc dec instructions

~15 a few instructions that are just declared illegal in 64 bit.

~30 size of push pop and the like instructions that have different logic based on the mode. Some 32 bit to 16 bit addressing in 64bit mode.

So ~64 of 256 = ~25% of the base instructions removed.

When you consider that most of the instructions dealing with all the other vector, complicated immediate mode operands and the like are already ModR/M provisioned. You're looking at ~64 / 65536 = 0.0029 = 0.03 % of the current operand map.

There may be some advantages gained by reduction in complexity of the instruction decoders, but considering everything is micro-op cached, another few micro %?

The one advantage you would get is mostly security based. The legacy modes often directly map interrupt and privilege escalations in unsafe ways.

 

[OneEng2]

Seems like "Intel is back" and it always surprises me seeing how much it consumes in power with so many cores.
I imagine that starting with Zen 6 AMD will also be forced to part large cores with a lot of compact cores to be able to keep the competition. But will AMD also be able to keep power consumption under control? The current design of an IOD fabbed on older process with CCDs will continue and work?

Intel doesn't appear to have an answer for Venice variants in DC. Ironically, Intel is looking strong in low end desktop and laptop, but still has no answer to AMD's HEDT and gaming solutions.

In other words, AMD is claiming all the most profitable markets and Intel is forced into lower margin, but higher volume markets.

Seems like Intel is falling behind from this POV.

 

[OneEng2]

On the subject of old instructions, I doubt the transistor count is worth a hill of beans 😉.

I think that Intel actually has it right with more specific extensions to raise IPC. It's my thought that moving forward we will have many more different kinds of CCD's that get mixed together for specific types of uses.

Right now we really have GPU core, big core, little core, and AI core.

 

[ETI4711]

There are other ones.
See

https://twitter.com/x/status/2038193892391289261

Like that:

stress_test - lscpu - OpenBenchmarking.org

openbenchmarking.org

it is 192 cores, one socket, 4 GHz max.

 

[StefanR5R]

I think that Intel actually has it right with more specific extensions to raise IPC.

SIMD extensions however are all about _low_ IPC. :-)

 

[Joe NYC]

SIMD extensions however are all about _low_ IPC. :-)

But, Single Instruction, Multiple Data takes place of multiple instructions on multiple data. So, in a sense, high IPC.