Question Zen 6 Speculation Thread

[marees]

Well, when adding SMT into the mix, it’s not really only fast vs slow cores, but fast vs slow threads we should be talking about.

The point was that once you go past 12T on 12C/24T Zen6, those additional threads will be SMT threads, which are much slower than e.g. E cores that some have been complaining about.

That depends on the task and resource bottlenecks right

Bulldozer was heavily bottlenecked by certain shared resources, I think

 

[MS_AT]

The point was that once you go past 12T on 12C/24T Zen6, those additional threads will be SMT threads, which are much slower than e.g. E cores

Anyone know how we could contact Chips and Cheese and ask if they could do an approachable explanation what SMT threads are?

But back on topic there are no "slow threads". You have two concurrent indepedent instruction streams, the slowness factor depends on if the streams are competing for the same resources or in other words it depends on the code. But the second instruction stream does not to be necessairly slower than the first running on the core.

 

[StefanR5R]

The point was that once you go past 12T on 12C/24T Zen6, [...]

The discussion was about games.

SMT threads, which are much slower than e.g. E cores

"much slower" #-)

Edit: Trick question: Back in the days when Intel's P+E hybrid CPUs still had Hyperthreading enabled in the P cores, in a situation when there were more runnable threads than P cores, was it preferable to schedule these extra threads on the E cores, or to schedule them on Hyperthreads of the P cores before spilling over to E cores? (And after that, we go back on topic of this thread and remind ourselves that throughput gains on AMD's SMT tend to be *at least* as high as on Intel's HT, in recent microarchitecture generations.)

 

[511]

Edit: Trick question: Back in the days when Intel's P+E hybrid CPUs still had Hyperthreading enabled in the P cores, in a situation when there were more runnable threads than P cores, was it preferable to schedule these extra threads on the E cores, or to schedule them on Hyperthreads of the P cores before spilling over to E cores? (And after that, we go back on topic of this thread and remind ourselves that throughput gains on AMD's SMT tend to be *at least* as high as on Intel's HT, in recent microarchitecture generations.)

The priority on ITD was P/E than P HT From what I remember you could always change that id you were Intel.

 

[maddie]

Anyone know how we could contact Chips and Cheese and ask if they could do an approachable explanation what SMT threads are?

But back on topic there are no "slow threads". You have two concurrent indepedent instruction streams, the slowness factor depends on if the streams are competing for the same resources or in other words it depends on the code. But the second instruction stream does not to be necessairly slower than the first running on the core.

True.

The fast/slow thread for SMT cores is an idea that refuses to die. Where is the silver bullet?

It's probably the fact that a SMT core gains 30-40% when running 2 threads and some assume that the 2nd thread gets that 30-40% leaving the original at 100%. False.

 

[eek2121]

Well, when adding SMT into the mix, it’s not really only fast vs slow cores, but fast vs slow threads we should be talking about.

The point was that once you go past 12T on 12C/24T Zen6, those additional threads will be SMT threads, which are much slower than e.g. E cores that some have been complaining about.

A 24 core Zen6 part will have more power available to them at a given power limit vs. a 48 core Intel part. This means that AMD cores will be able to clock higher.

Remember that the Intel parts will likely have much lower clock speeds for at least 32 of the cores as well.

I expect AMD will win most benchmarks and only lose a few. I don’t expect Intel will have a decent part until they unify the cores/do a rework.

 

[adroc_thurston]

A 24 core Zen6 part will have more power available to them at a given power limit vs. a 48 core Intel part. This means that AMD cores will be able to clock higher.

Remember that the Intel parts will likely have much lower clock speeds for at least 32 of the cores as well.

I expect AMD will win most benchmarks and only lose a few. I don’t expect Intel will have a decent part until they unify the cores/do a rework.

Moreover it's 2 shrinks worth of PPW for AMD and 1 for Intel.

 

[511]

Moreover it's 2 shrinks worth of PPW for AMD and 1 for Intel.

1.5 according to TSMC

 

[adroc_thurston]

1.5 according to TSMC

N2 is a full node perf/power wise.

 

[511]

N2 is a full node perf/power wise.

N4P -> N3E is half node according to TSMC graphs N3E -> N2 yes I agree

 

[adroc_thurston]

N4 -> N3E is half node according to TSMC

It's also a full node shrink.

 

[511]

Not in PPW and from TSMC Figures in density it is for sure

 

[adroc_thurston]

Not in PPW and from TSMC Figures in density it is for sure

Yes in PPW.
More so if you do 3-2 finflex where it goes zoom zoom.

 

[OneEng2]

It's basically what drives DIY demand.

Yes, but my point is that ALL of desktop is ~ %30 of the x86 market. DIY is about 10-20% of that 30% ..... or 6%.

So gaming is likely a percentage of 6% (maybe a high percentage?), but still, somewhere south of 6%.

So why is it so important?

 

[adroc_thurston]

Yes, but my point is that ALL of desktop is ~ %30 of the x86 market. DIY is about 10-20% of that 30% ..... or 6%.

And

So why is it so important?

Fat margins tied to an install base both loyal (as long as you keep winning) and ready to pay them.

 

[adroc_thurston]

In any case, AMD's core/fabric/analog/whatever IP roadmaps are driven by server socket perf CAGR.

 

[OneEng2]

That depends on the task and resource bottlenecks right

Bulldozer was heavily bottlenecked by certain shared resources, I think

Yes it most surely was.

Zen 5's SMT implementation is quite good adding only 5% transistor budget and achieving ~40% (DC) in MT performance.

A 24 core Zen6 part will have more power available to them at a given power limit vs. a 48 core Intel part. This means that AMD cores will be able to clock higher.

Remember that the Intel parts will likely have much lower clock speeds for at least 32 of the cores as well.

I expect AMD will win most benchmarks and only lose a few. I don’t expect Intel will have a decent part until they unify the cores/do a rework.

I think that everyone needs to start warming up to the idea that Zen 6 desktop is going to get walloped by NVL 52c in MT testing.

For ST (or low thread count), I suspect you are correct.

 

[OneEng2]

And

Fat margins tied to an install base both loyal (as long as you keep winning) and ready to pay them.

Agree on the fat margins, but it's still likely only around 3-4% of overall sales. Bragging rights are also good.

In any case, AMD's core/fabric/analog/whatever IP roadmaps are driven by server socket perf CAGR.

Absolutely agree.

The biggest growth and highest margins are in DC. AMD is smart to focus designs in this area IMO.

 

[511]

More so if you do 3-2 finflex where it goes zoom zoom.

N4P HP Exists though for zoom zoom on N4

 

[adroc_thurston]

Agree on the fat margins, but it's still likely only around 3-4% of overall sales

Higher.

The biggest growth and highest margins are in DC. AMD is smart to focus designs in this area IMO.

Less that and more like it's a market they can win on all metrics just by sticking to what they do best.

N4P HP Exists though for zoom zoom on N4

No one uses that.
And in any case, it's still a full shrink in all dimensions via 3-2 FF

 

[jpiniero]

Yes, but my point is that ALL of desktop is ~ %30 of the x86 market. DIY is about 10-20% of that 30% ..... or 6%.

So gaming is likely a percentage of 6% (maybe a high percentage?), but still, somewhere south of 6%.

So why is it so important?

The other 93% pretty much only cares about Chrome and Office.

 

[Thunder 57]

N4P HP Exists though for zoom zoom on N4

Oh no are you starting to speak Adroc?

 

[Fjodor2001]

That depends on the task and resource bottlenecks righ

Yes, agree. And context was gaming.

 

[Fjodor2001]

Anyone know how we could contact Chips and Cheese and ask if they could do an approachable explanation what SMT threads are?

You know what I mean. No need to intentionally try to misunderstand.

But I'll school you since you asked for it:

For 12C/24T, at up to 12T basically you won't be using SMT since there'll only be one T per C. When going above 12T, additional threads will have to share core with some other thread. So perf/thread will be lower compared to when only having 1 T per C. So you can call those two threads sharing the same core SMT threads or whatever. Does not matter what you call it. Of course they are all just threads in OS context. But the point is that those two threads will be sharing the resources of one core, so they won't be executing as fast as threads which have a core dedicated to them and do not share it with other threads.

And main point: Those SMT threads (or whatever you want to call them) will be executing slower than threads on E cores (and P cores too of course!). Because threads on E cores do not share the E core with other threads, since E cores do not use SMT/HT.

 

[Fjodor2001]

The discussion was about games.

Yes

"much slower" #-)

Yes

Edit: Trick question: Back in the days when Intel's P+E hybrid CPUs still had Hyperthreading enabled in the P cores, in a situation when there were more runnable threads than P cores, was it preferable to schedule these extra threads on the E cores, or to schedule them on Hyperthreads of the P cores before spilling over to E cores?

We're talking about NVL E core level of perf, not history.