So you are saying that's the only CPU instruction that the CPUs are executing?
"e.g." is shorthand for "for example".
In favourable circumstances for Intel it will be the case. Think Cinebench vs Y-cruncher. E cores have more but narrower execution units (4fma per cycle vs 2 on zen) so if software uses mostly scalar or narrow simd E cores might have a lead.
Thanks! I actually wanted to look up what the respective backends are equipped with (in the latest gen, assuming the upcoming gen will be similar) but then didn't go through with it. Now, the immediate next question would be about the energy consumption of the FMAs while they can be kept busy. Apparently this can only be answered satisfyingly after these CPUs actually become available.
And when we are past the questions of backend width and backend power requirements, we quickly get to the question of how well the frontends and the memory subsystems can keep these top end desktop CPUs utilized... So I stick with my idea that Fjodor2001 is a bit hastily getting to his conclusions.
PS, re Cinebench in particular: I have no doubt that those users who run Cinebench 24/7 are best served by the one CPU vendor who has been equipping his last several CPU generations with a dedicated Cinebench accelerator block. ;
-) PPS, I admit to a personal bias to engineering/scientific use cases when it comes to CPU discussions.
Also, note that it may not only be a single App you’re using. You could e.g. be transcoding movies, compiling source code, running some anti-virus Sw, OS maintenance tasks, and watching movies / web pages or reading email, all at the same time. Most of those workloads can be executed in the background, and only the last few ones require human interaction.
Sounds like a lot of I/O waiting and cache thrashing.
I find AM5 meeting all my needs for I/O but I could use more cores from time to time
Several years back, when I personally started to need more cores for the first time (until then I only had use for faster cores, not more cores), I also needed proportionally more memory channels. (Plus better-than-Gigabit-Ethernet interconnect for spreading one application instance across the total available number of memory channels. It was for engineering work.)