Question Zen 6 Speculation Thread

[Hulk]

While it is possible that there will be bandwidth limits, or latency limits, etc, etc.

This.

I would add that it's one thing to have a lightly loaded core crank up the frequency for a few seconds and then back down. That's how Raptor Lake would behave. Unless you had a monster custom loop, 6GHz sustained clocks on multiple cores for was impossible due to thermal/power limitations.

Currently, and I have to check, but I think my 280AIO/9950X only does around 5GHz when getting slammed by something like Cinebench, when I'm heavily multitasking. CB, while not realistic, can "sub in" for heavy multitasking. Anyway, back to my point, a "real" 10% clock speed bump for Zen 6 would be sustaining 5.5GHz for 16 of the supposed 24 cores while using the same power/thermal envelope as Zen 5.

So while I don't doubt the increased frequency and especially power efficiency of the new node, when I hear 6GHz or higher I'm thinking under what cooling solution, how many cores loaded, and how heavily loaded are they? That is currently an overclocking target for Zen 5 and a tough one at that. Zen 6 getting there "out-of-the-box" and by that I mean like a 360AIO even would be seriously impressive, especially when you consider a 50% increase in core count and increased IPC.

 

[Joe NYC]

That is one hell of a wish list. Two stacks of cache and 7GHz ? I could imagine the marketing though. Zen 7 featuring 7GHz launching 7/7! Also as has been mentioned diminishing returns would likely hit hard.

I think longer term answer is L3 cache + V-Cache to go fully off die, to run at half speed. There is already latency of several clocks for L3 and then another 1-2 clocks for V-Cache. Going to half speed just adds 1 clock to that latency.

Which is a small penalty, vs. the gains (in enabling greater ease of throwing more silicon at it). BTW, I would not be surprised if Zen 5 is already doing it.

 

[Win2012R2]

I think longer term answer is L3 cache + V-Cache to go fully off die, to run at half speed.

What would be the gain of going half speed - faster CPU clocks since they won't rely on cache being in sync?

If so why would it be just 1 clock delay when you go half speed?

 

[511]

You must be joking. 1T is more difficult than MT easily. You can just spam cores and add power to win at MT with a halfway decent design.

With Intel's strategy it won't be difficult cause P core exists for that reason if they fail to it that's a P core skill issue.
In ARL Skymont is basically Carrying it for the most part.

 

[Joe NYC]

Don't you mean "cache-ing" up?

Sorry, I know that's terrible but I couldn't resist.

Cache me outside, how about that, ho?

 

[Joe NYC]

What would be the gain of going half speed - faster CPU clocks since they won't rely on cache being in sync?

Ability to continue to use inexpensive die for cache, which can't match the clock speed of the CPU die,

The progression was:
- Zen 3: N7 base die, N7 V-Cache
- Zen 4: N5 base die, N7 V-Cache
- Zen 5: N4 base die, N7 (or N6) V-Cache

Disparity gets too great if Zen 6 is to run at 6.5 GHz on N2. Going to N4 for V-Cache die not only adds cost, there is still a huge traffic jam on the N4 node, with very strong demand and limited capacity.

This high demand of N4 with limited capacity may just be starting to ease when Zen 6 is released, but it is too close for comfort. AMD might want to stay with N7/N6 for V-Cache die - node where the capacity is endless.

If so why would it be just 1 clock delay when you go half speed?

The bandwidth is practically unlimited with Hybrid Bond, so you can transmit 2x data every other clock.

 

[Thunder 57]

Cache me outside, how about that, ho?

Well because of this show, idiots, and who knows what else that dumbtard made $1 million in six hours a few years later. More proof that "idiocracy" is indeed a documentary.

 

[DrMrLordX]

Wait, no one wants an asymmetric premium desktop product design?!?! How the heck does AMD justify producing the 9900/9950X3D then?

That's not really the same thing . . .

 

[adroc_thurston]

After Strix Point, AMD proved that there is nothing logical or technical stopping them from having two VERY different CCXs in the same package

Dawg we're back to uniclusters across Medusa pmuch.

 

[Joe NYC]

Dawg we're back to uniclusters across Medusa pmuch.

Do you mean to include in that unicluster with different types of cores, in MDS1 die?

BTW, do you know if the different cores on Kraken are on the same ring bus? Grok seems to think Yes, but there is no official confirmation stating this.

It would be sub optimal to separate them, which is why Strix Point is such an odd CPU.

 

[adroc_thurston]

Do you mean to include in that unicluster with different types of cores, in MDS1 die?

Yea.

BTW, do you know if the different cores on Kraken are on the same ring bus

Yea.

 

[StefanR5R]

first I want to see what they actually come up with. 2nd, whatever it is I am sure AMD will counter it with something. I mean 52 cores that will almost blow most power supplies is what I am guessing we will see, if anything at all. 2nd, AMD will have 24 cores with SMT or 48 effective, probably at 200 watts or less.

Of these rumored 52 cores, 4 do not pull any power to speak of: They are low-power cores for background load/ near idle scenarios. These cores exist for battery powered devices. Intel could just as well fuse these cores off in desktop SKUs. But maybe they won't for marketing purposes.

I think it is unrealistic to expect a 24c Zen 6 to keep up with a 52 core NVL in applications that scale well with the number of cores .... at least on the surface.

So let's look just a hair's breadth beneath the surface.

• Intel's rumored top desktop CPU runs either up to 8+8 fast threads or up to 48 throughput threads.
• AMD's rumored top desktop CPU runs either up to 12+12 fast threads or up to 48 throughput threads.

From that, it is not hard to extrapolate the likely behaviour of programs which scale better or worse on such CPUs.

 

[LightningZ71]

Dawg we're back to uniclusters across Medusa pmuch.

Except for Medusa Premium, which can have one 12 core CCX on N2, and another 8 core CCX made up of 4 x P cores and 4 x C cores? Unless you are suggesting that they extend the CCX between both dies, which seems like it would be a very bad idea for a lot of reasons...

 

[Fjodor2001]

• Intel's rumored top desktop CPU runs either up to 8+8 fast threads or up to 48 throughput threads.
• AMD's rumored top desktop CPU runs either up to 12+12 fast threads or up to 48 throughput threads.

Difference is that Intel's vs AMD's throughput threads are different animals, because the latter one uses HT/SMT.

 

[Chicken76]

Well because of this show, idiots, and who knows what else that dumbtard made $1 million in six hours a few years later. More proof that "idiocracy" is indeed a documentary.

1 Million?! Who? How? When?
Idiocracy© was awsome I agree. Hard to believe it came out almost 20 years ago.

 

[adroc_thurston]

Except for Medusa Premium, which can have one 12 core CCX on N2, and another 8 core CCX made up of 4 x P cores and 4 x C cores?

that's MDS1 and the non-CCD CCX gets offed in the CCD variant.

 

[CouncilorIrissa]

After Strix Point, AMD proved that there is nothing logical or technical stopping them from having two VERY different CCXs in the same package. They may have to make a unique substrate package that has different traces to support the different CCDs, so it certainly won't be a cheap product, but it's certainly doable.

I dare say that if there's a market for an Intel core processor with 16 P cores and 32 e cores, there also exists a market for an AMD product with a 12 core Zen 6 CCD and a 32 core Zen6c CCD. That market may not make a pick of sense except for bragging rights, and may not support the differential cost of it's products, but it certainly is a market.

Ehh. Strix Point had tons of scheduling issues on launch. Pretty sure Arrow did as well, and that thing has a Thread Director which is supposed to help with that.

 

[Philste]

that's MDS1 and the non-CCD CCX gets offed in the CCD variant.

Really? So Medusa 1 actually tops out at 12×ZEN6 instead of the rumored 16×ZEN6 + 4×ZEN6c?

 

[adroc_thurston]

So Medusa 1 actually tops out at 12×ZEN6 instead of the rumored 16×ZEN6 + 4×ZEN6c?

Yeah.
Also there's a 2c LP cluster either way.

 

[luro]

Of these rumored 52 cores, 4 do not pull any power to speak of: They are low-power cores for background load/ near idle scenarios. These cores exist for battery powered devices. Intel could just as well fuse these cores off in desktop SKUs. But maybe they won't for marketing purposes.

So let's look just a hair's breadth beneath the surface.

• Intel's rumored top desktop CPU runs either up to 8+8 fast threads or up to 48 throughput threads.
• AMD's rumored top desktop CPU runs either up to 12+12 fast threads or up to 48 throughput threads.

From that, it is not hard to extrapolate the likely behaviour of programs which scale better or worse on such CPUs.

Yeah. At the end it’s going to be 48 vs 48. That 4LPE will just make any difference in the marketing presentations

 

[Josh128]

I mean, 6GHz+ is a given, otherwise, the whole AMD CPU division should be fired in the act. It's a double node jump and even if it would only use N3P or N3X, 6GHz is only a 5% increase.
The question here is not 6GHz+, but if it can clock to 6.5GHz or more. I think 6.5GHz will happen, i don't think much more than that, though, and I think 7GHz is a pipe dream.

Nothing is a given.

 

[Josh128]

Yes, first I want to see what they actually come up with. 2nd, whatever it is I am sure AMD will counter it with something. I mean 52 cores that will almost blow most power supplies is what I am guessing we will see, if anything at all. 2nd, AMD will have 24 cores with SMT or 48 effective, probably at 200 watts or less. I mean just Zen 5, I have 128 cores with 256 effective at less than 500 watts.

Lets just see what the actual products come up with.

Zen 6 24C will almost certainly top out over 200W. It will likely max out AM5 power delivery, whatever that is. Zen 4 was 230W PPT, so I'd bet the farm that Zen 6 24C will be at least that, possibly a bit more if the socket can handle it.

 

[Josh128]

Why do you think they have to? They seem to be doing fine on N4P while Intel is on N3B (which is an even better node than N3E aside from cost).

It's an interesting question. How power efficient was an e core on N3B? How much improvement should we expect moving from N3B to N2? Certainly not anything like AMD moving from N4P (an N5 variant) to N2. Still, it wasn't like Skymont cores were sucking power .... but double the cores?

A lot of people here are claiming N3B is barely any better than N4P. If thats the case, then Intel going from N3B to N2 is going to be very close to the same jump that AMD is getting going from N4P to N2. Cant have it both ways.

 

[Joe NYC]

Except for Medusa Premium, which can have one 12 core CCX on N2, and another 8 core CCX made up of 4 x P cores and 4 x C cores? Unless you are suggesting that they extend the CCX between both dies, which seems like it would be a very bad idea for a lot of reasons...

These are 2 separate dies, so clearly not.

 

[LightningZ71]

Yeah.
Also there's a 2c LP cluster either way.

Wait, Does MDS1 have a bespoke IOD, or is it really using a Medusa Monolithic chip with the CPU CCX fused off? Unless they are expecting a whole lot of die recovery needed, that seems like a massive waste of silicon... The earlier rumor was that Medusa's normal die (4P+4C+4WGP) also had the link for an external CCD and that the premium product was going to be a 12 core CCD attached to that 4+4+4 SOC.