Question Zen 6 Speculation Thread

[511]

Well, for what it's worth, L3/SRAM scaling on all of TSMC's non-specialized libraries from N5 all the way to N3E have had a big fat zero in SRAM scaling improvement.
N2 is the first node after a long time that improves on it. A relatively generous ~17% shrink.

I'm betting this was one of the big factors in AMD wanting to splurge all-in for N2 across the board with Zen6 designs.
You can have your extra cores shrink all you want for your CCDs, they're tiny anyway, but if that 24/48MB/64MB/whatever L3 needs 50% more die space, that ain't good.

There is no bitcell shrink it's a SRAM Macro Shrink.

 

[LightningZ71]

It's PRIMARILY a macro shrink, but, there is a little bit-cell shrinkage in N2. BSPDN should manage to shrink the macro a bit once it's implemented due to relocating the power wires. I think Tom's had an article that gave a bit more detail. If memory serves, the shrinkage is not advertised as a benefit due to how small it is, and is largely math extrapolated from other published numbers.

Until they go 3D with the cells, find a way to make 4T work well enough in current applications, or reimagine the whole cell to take better advantage of lithography changes over the last decade, it's not shrinking much more.

 

[511]

but, there is a little bit-cell shrinkage in N2

there is none according to TSMC

 

[Thunder 57]

there is none according to TSMC

From the same source as Adroc?

 

[adroc_thurston]

there is a little bit-cell shrinkage in N2

Nnnnope.

From the same source as Adroc?

They did publish N2 stuff at like ISSCC iirc.

 

[511]

From the same source as Adroc?

https://twitter.com/x/status/1892246045385515266

 

[adroc_thurston]

https://twitter.com/x/status/1892246045385515266

see my memory wasn't wrong, it was ISSCC.

 

[511]

see my memory wasn't wrong, it was ISSCC.

lol i knew that

 

[OneEng2]

For the record let me just say that I never said anything about Zen 6 classic being limited any specific number of core counts until I was told by someone else that I did. After which I only questioned why it would drop from current Zen 5 counts.

Apparently I missed this roadmap leak everyone is talking about. The most recent one I can find is the one for mobile mentioning "Gator Rande".



View attachment 130437

Yea, the leak they are talking about showed some IOD configurations and people extrapolated to the core counts. I don't believe that AMD has stated what core counts will be supported for full Zen 6.

96 Zen 6 Core would likely be limited to SP8 and 8 Ch memmory and 256C would require SP7 you can easily pack 8 Zen6 CCX and it doesn't require 16 Ch memory.

I still am not seeing the logic behind going from 128 full Zen 5 cores to 96 Zen 6 cores. For workloads that need the higher performance cores, there is no way this ISN'T a step backwards ..... which again simply doesn't make any sense.

I will be delighted to look back on this thread and either state "See, it didn't make any sense", or "Wow. You were right"; however, at this time, I am in the "It doesn't make any sense" camp.

 

[adroc_thurston]

I still am not seeing the logic behind going from 128 full Zen 5 cores to 96 Zen 6 cores

Because you're going from 64c Z5c of Sorano to 96c Z6 for Venice SP8.
SP5 Turin Classic has no successor.

 

[Markfw]

Because you're going from 64c Z5c of Sorano to 96c Z6 for Venice SP8.
SP5 Turin Classic has no successor.

My 9755 is absolutely kicking ass in the current DC competition that is very avx-512 dependant. And at 100% load its doing 64 c CPU temp WITH AN AIR COOLER !
You can't say enough good things about Turin,.

 

[LightningZ71]

I think that people are failing to see the big change for this generation and not seeing where it will make the most difference. The "c" core CCD is rumored to have the same total amount of L3 cache as the normal core CCD. It's still less per core, but the total local pool is much larger. In addition, with the node improvement, even if just from N3, you still get a notable improvement in throughput per watt. I suspect that, in many cases, 128 cores of Zen 6c will be faster than regular Zen5, and I don't think that there will be a notable difference in all core steady state clocks under load with Zen6 possibly doing better.

 

[CouncilorIrissa]

I think that people are failing to see the big change for this generation and not seeing where it will make the most difference. The "c" core CCD is rumored to have the same total amount of L3 cache as the normal core CCD. It's still less per core, but the total local pool is much larger. In addition, with the node improvement, even if just from N3, you still get a notable improvement in throughput per watt. I suspect that, in many cases, 128 cores of Zen 6c will be faster than regular Zen5, and I don't think that there will be a notable difference in all core steady state clocks under load with Zen6 possibly doing better.

That's already the case with Turin-D, the dense CCD has 32MB of L3.

 

[adroc_thurston]

The "c" core CCD is rumored to have the same total amount of L3 cache as the normal core CCD

No?
Dense is 128M, classic is 48M L3$.

In addition, with the node improvement, even if just from N3, you still get a notable improvement in throughput per watt

they're all N2p.

 

[gdansk]

OFFICIAL FAN SLIDEWARE for ZEN 6 (Desktop)
Comments, concerns?
I believe we have this nailed.

 

[adroc_thurston]

View attachment 130533
OFFICIAL FAN SLIDEWARE for ZEN 6 (Desktop)
Comments, concerns?
I believe we have this nailed.

boring, fix your numbers

 

[gdansk]

boring, fix your numbers

After painstakingly reviewing paint I remain confident these are the best numbers. I am not a fan of 42% personally.

 

[adroc_thurston]

I am not a fan of 42% personally.

you're getting 70% moar for Venice doe.
so fix your numbers.

 

[blackangus]

OFFICIAL FAN SLIDEWARE for ZEN 6 (Desktop)
Comments, concerns?
I believe we have this nailed.

You forgot:
1: Or less
2: In the arctic circle

 

[adroc_thurston]

You forgot:
1: Or less
2: Maybe

and need a bulletpoint for gen3 Vcache.
Ain't no way AMD's not gonna dangle the crackpipe in front of thirsty-thirsty gamers.

 

[LightningZ71]

No?
Dense is 128M, classic is 48M L3$.

That's considerably more than I expected. So, that's the same L3 per core...

they're all N2p.

I meant going from Zen5p ccd to Zen6c CCD, that's going from N4x/p to N2. That's quite a jump...

 

[adroc_thurston]

So, that's the same L3 per core...

Yeah, favelas wanted that.

I meant going from Zen5p ccd to Zen6c CCD, that's going from N4x/p to N2. That's quite a jump...

You're jumping to N2p for everything but mainstream mobile parts.

 

[soresu]

and need a bulletpoint for gen3 Vcache.
Ain't no way AMD's not gonna dangle the crackpipe in front of thirsty-thirsty gamers.

V cache at this point interests me for one reason, and one reason only.

That being the possibility of a future generation completely eliminating L3 (and possibly even L2) cache off the main logic die.

Honestly when MLID started blarting about a 3D core for Zen7, this is what I was assuming he was talking about.

 

[adroc_thurston]

That being the possibility of a future generation completely eliminating L3 (and possibly even L2) cache off the main logic die.

yeah.

Honestly when MLID started blarting about a 3D core for Zen7, this is what I was assuming he was talking about.

oh nooo 3D core is something wayyyyy different. Forget about it for a moment.

 

[gdansk]

That being the possibility of a future generation completely eliminating L3 (and possibly even L2) cache off the main logic die.

Intel has been trying to make this work for a certain forest for years now. Lots of slideware available on that.