Josh128
Golden Member
- Oct 14, 2022
- 1,318
- 1,983
- 106
What are you basing that on, personal conviction?
Heres some hard numbers from GN Blender testing.
12 core 7nm 5900X@ 105W TDP: 11.3 seconds
16 core 5nm 7950X@105W TDP: 6.4 seconds
Thats a 77% speed increase at the same power for a single node jump and only 33% more cores.
A 24 core Zen 6 has 50% more cores and a double node jump over a 9950X. What would lead you to believe its going to have less potential MT perf increase than the example above, even at iso power?
Last edited:
With 45% lower power from the process that make 110W for a theorical 2nm based 9950X and 165W for a 24C/48T.
With 11% better IPC that set the bar at 165 x 1.11 = 183W for 1.5 x 1.11 = 1.665x the MT perf.
Assuming that they get back to 230W PPT this allow to exploit 47W to increase the perfs at the expense of 230/183 = 1.256x the power, wich should increase the clocks by 8%
and hence get to 1.665 x 1.08 = 1.8x the perfs of a 9950X, so 75-80% seems a reasonable estimation.
Last edited:
Josh128
Golden Member
- Oct 14, 2022
- 1,318
- 1,983
- 106
TSMC claimed N3 is 25%-35% more efficient and 70% more dense than N5.
TSMC claimed N2 is 25%-30% more efficient and 15% more dense than N3.
Using these numbers, worst case scenario efficiency is N5 x 1.25 x 1.25= 1.56% better efficiency vs N5. Being that 9950X uses N4, you can probably assume 1.45x better efficiency. N5 was claimed to have 30% better efficiency than N7, so going by that, you should see quite a bit better MT increase than my 105W 5900X vs 105W 7950X above, which was 77%.
TSMC claimed N2 is 25%-30% more efficient and 15% more dense than N3.
Using these numbers, worst case scenario efficiency is N5 x 1.25 x 1.25= 1.56% better efficiency vs N5. Being that 9950X uses N4, you can probably assume 1.45x better efficiency. N5 was claimed to have 30% better efficiency than N7, so going by that, you should see quite a bit better MT increase than my 105W 5900X vs 105W 7950X above, which was 77%.
45% lower power = 126W assuming 230W PPT for 9950X 189W for 24C. Assuming 10% more power for IPC improvement roughly 207W and than 23W I since performance scaling is not going to be linear at such power level roughly 1.05X so 1.73X MT.
There was a massive increase in frequency when comparing N7 to N5 do you think there will be same frequency increases a 5900X. Do you think there will be 15-18% jump in peak frequency?
I don't think so I expect 10-12% frequency improvementa.
This density is 1.6X vs N5 but this is N4P which is 11% perf/watt increase vs N5 and 6% Denser than N5.
For N2 you are correct
There s nothing to assume since the number is known, 9950X has a 200W PPT, i thought it was common knowledge.
170*1.35 = 229
Edit: Looks like you remembered it wrong.
PL is not always TDP * 1.35.
For example, I can confirm 9950X3D out of the box is 200W PPT despite 170W TDP:
What is the power consumption 200W as well cause I checked few sites and have seen 220-230W.
Total system draw was lower when running CB than my 7950X. But I have no other metrics than what my UPS and hwinfo report.
It is simple: 128C is not required with "P" cores
- 96C will clock higher, which is better for many applications. 128C+ SKUs / Applications / Use-Cases will not require super high ST performance in very most cases
- Same applies for any V-Cache SKU and use case
- Zen 6c in N2 hits probably quite decent clock rates, let's say 4.5+ GHz instead of 3.7 GHz of Zen 5 (N2 FinFlex / NanoFlex for the win; 2nd generation "c" cores and respective learnings)
- 128C SKUs will probably not hit >4.5 GHz (EPYC 9755 peaks at 4.1 GHz)
- 4.5 GHz Zen 6 kills already all Zen 5 EPYC SKUs as well as any Intel counterpart in ST Benchmarks (5.0 GHz max. on F-SKUs compared to Zen 6 with >10% IPC increase) --> Good enough
- Zen 6c features the full amount of L3-Cache (128 MByte per 32C chiplet)
So there you have it:
No reason for the "P" Cores. You can deliver 128C Zen 6 with 32C Chiplets. This will be cheaper and probably more energy efficient. And if you like (and memory bandwidth / PCIe Lanes are not important for you) also with one IOD (8ch memory saves space in your server rack).
Zen 7 might increase then from 12C to 16C and you have additional +33% cores and 128C with "P" cores again
Workload does not change the PPT. That requires system reconfiguration. Here's prime95. It's still 200W. I simply want the facts here. PPT for Zen 5 is not always 1.35 x TDP. Default PPT for 9950X and 9950X3D is 200W. You may change it, some may have done so. I cannot say what PPT the review you're looking at actually used, they should disclose if they changed things. But 200W is AMD's default.
It wont go over 200W even with Prime 95, those sites are likely measuring the CPU 12V rail current that include the VRMs losses.
Where is this magical gain coming from we are comparing N3E to N2/N2P not N4P to N2 it's likely going to be 4-4.2Ghz.
Regarding the maximum core count of Zen 6 server:
Remember that there will be (according to rumors) two big-socket platforms,
– SP7 with 16 DDR5 channels per socket,
– SP8 with 8 DDR5 channels per socket.
Zen 6-dense CCDs will certainly be used on SP7.
I don't recall if anything was said yet whether or not Zen 6-dense CCDs (with 32-cores complexes) will also go onto SP8, nor if anything was said yet whether Zen 6-classic CCDs (with 12-cores complexes) will go into both or only into one of SP8 and SP7.
The target markets for SP7 and SP8 respectively will not be quite the same as SP5's and SP6's, is my impression.
(Edit: Or it'll be three big-socket platforms actually, if we also count MI400's socket. MI300A/C/X are sitting in socket SH5. I am not aware of any signs though that a MI400 variant with CPU cores is on the horizon.)
Remember that there will be (according to rumors) two big-socket platforms,
– SP7 with 16 DDR5 channels per socket,
– SP8 with 8 DDR5 channels per socket.
Zen 6-dense CCDs will certainly be used on SP7.
I don't recall if anything was said yet whether or not Zen 6-dense CCDs (with 32-cores complexes) will also go onto SP8, nor if anything was said yet whether Zen 6-classic CCDs (with 12-cores complexes) will go into both or only into one of SP8 and SP7.
The target markets for SP7 and SP8 respectively will not be quite the same as SP5's and SP6's, is my impression.
(Edit: Or it'll be three big-socket platforms actually, if we also count MI400's socket. MI300A/C/X are sitting in socket SH5. I am not aware of any signs though that a MI400 variant with CPU cores is on the horizon.)
Last edited:
Josh128
Golden Member
- Oct 14, 2022
- 1,318
- 1,983
- 106
nT frequency is not at all reliant on fmax. It is much more reliant on transistor / node efficiency. 7950X/9950X all core boost is ~5GHz at stock power limits according to GN tests. If N2 allows for 5.5 all core boost, that would be a 10% increase, that is still well below fmax.. A 5900X all core boost is around ~4.5GHz, which is only 10% lower than the 7950X nT frequency. The 7950X achieved +77% nT Blender perf over 5900X at 105W, which would not even be at its max nT frequency of +11% over 5900X. In any case, even the most conservative "leaks" so far indicate AMD is targeting a significant fmax increase for Zen 6, so +10-15% nT increase is a perfectly reasonable expectation.
So yeah,, I do think nT frequency can achieve more than a 10% bump-- but ~10% is all that would be required to achieve such results. Less, actually, because you are talking 33% more cores in the 5900X to 7950X ECO mode comparison when we know that the new flagship will have a 50% more cores advantage vs 9950X.
Josh128
Golden Member
- Oct 14, 2022
- 1,318
- 1,983
- 106
Its coming from TSMCs claims that its a 10%-15% boost in computing speed at the same power level or a 20-30% reduction in power usage at the same speed vs N3E, which already has been proven to clock as well as N4P. See Arrow Lake 285K 5.7GHz boost.
I am comparing N3E Zen 5C vs N2 Zen 6C like you said so even 15% is 4.25 not 4.5+ on 6C also N3E clocks a bit higher than N3B
Magic / secret sauce
Some thoughts:
- N2 vs. N3 is a similar step as N3 vs. N4 -> +15% -> 3.3 GHz on 370 HX vs. 3.7 GHz on EPYC --> your 4...4.2 GHz are reasonable from N2 process alone
- Zen 6 design generally geared towards Fmax rather than max. IPC -> speculation, but could yield in additional cloch rate gains
- 2nd generation "c" cores -> Pimp your critical paths -> speculation as well (but reasonable), get some additional clock rate gains
- More power per core -> Advanced packaging, new IOD and probably higher TDPs
- 1.7x performance for the 256C vs. 192C Zen 5 SKU -> 1.7x / 1.33x = 1.28x -> Very likely not all IPC, so clock rates will increase by quite some bit even at max. core count. So a 128C SKU could use its TDP and clock even higher.
I do not see any huge blocking points for 4.5 GHz. It is a mere +10% what N2 should be delivering. Sure, it will not be for free. But it is not unreasonable.
adroc_thurston
Diamond Member
- Jul 2, 2023
- 7,067
- 9,808
- 106
Oh no it's aimed for moar fmax, N2 is just a good shrink to play around with.
This is a all core benchmark not peak and ~10-11% IPC over a 2 years is not a tall order
TRENDING THREADS
-
Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)- Started by DisEnchantment
- Replies: 25K
-
Discussion Intel Meteor, Arrow, Lunar & Panther Lakes + WCL Discussion Threads
- Started by Tigerick
- Replies: 22K
-
News NVIDIA and Intel to Develop AI Infrastructure and Personal Computing Products- Started by poke01
- Replies: 384
-
Discussion Intel current and future Lakes & Rapids thread- Started by TheF34RChannel
- Replies: 23K
Facebook
Twitter