Question Zen 6 Speculation Thread

[Antey]

If AMD and intel start to intruduce ''big APUs'' to the PC market. isn't it possible that they decide that low-mid MOBOs don't need a PCIe slot for an external GPU because they wouldn't be adding that many pcie lanes to their APUs... threatening NVIDIA gaming GPUs?

Why would you want to buy a X050-X070 NVIDIA GPU if to do that you need to buy a very very expensive high end mobo and a very expensive hig end CPU with enough pcie lanes, but you can buy a cheap MOBO + a not-so-cheap big APU if you want a gaming PC? or a cheap mobo and a cheaper cpu with an smaller iGPU for office.

 

[MS_AT]

If AMD and intel start to intruduce ''big APUs'' to the PC market. isn't it possible that they decide that low-mid MOBOs don't need a PCIe slot for an external GPU because they wouldn't be adding that many pcie lanes to their APUs... threatening NVIDIA gaming GPUs?

I guess nVidia is safe for the time being as long as it holds a lead in discreet market. The reason being, why would you want to have a gaming PC without nVidia GPU? [seems from observation that is dominating mindset in the gamer community].

Why would you want to buy a X050-X070 NVIDIA GPU if to do that you need to buy a very very expensive high end mobo and a very expensive hig end CPU with enough pcie lanes, but you can buy a cheap MOBO + a not-so-cheap big APU if you want a gaming PC? or a cheap mobo and a cheaper cpu with an smaller iGPU for office.

At the same time nVidia wants to bring it's own iGPUs paired with ARM cores, basically cutting off AMD and Intel from the market (if they succeed that is, and right now they have problems with pushing N1X out of the door... ). So might be that nVidia will be able to provide the APUs too.

 

[StefanR5R]

@Antey, a not-so-cheap APU needs high memory bandwidth. Otherwise its performance potential would go to waste, and it would stand no chance against low end dGPUs, let alone mid range dGPUs. The cost of high memory bandwidth are: Higher mainboard cost (in other words: the combo of cheap mainboard and not-so-cheap APU is not realistic), and a tendency to higher memory latency (to the detriment of client CPU workloads).

 

[LightningZ71]

Higher implementation costs for "big" APUs can be offset by mainboard simplification. With a decent GPU already present, the PEG slot can disappear. LPDDRX RAM is typically soldered, so no RAM slots anymore. With a couple of USB4/TB5 ports, there's no real need for even PCIe 1x and 4x slots for the vast majority of the market. Now, all you have on the mainboard are I/O ports on the edges, pin headers, and a couple of NVME slots, making them much smaller. Less materials all around.

I suggest that the micro-boxes for Strix HALO and the hand helds are a sign of where the market is going. They don't have a lot of total volume right now, but there is a good variety of those products available out there. There's also the ever increasing volume of uSFF desktops in corporate as a share of the desktop market. These things are going more and more towards just static, disposable boxes.

 

[marees]

Higher implementation costs for "big" APUs can be offset by mainboard simplification. With a decent GPU already present, the PEG slot can disappear. LPDDRX RAM is typically soldered, so no RAM slots anymore. With a couple of USB4/TB5 ports, there's no real need for even PCIe 1x and 4x slots for the vast majority of the market. Now, all you have on the mainboard are I/O ports on the edges, pin headers, and a couple of NVME slots, making them much smaller. Less materials all around.

I suggest that the micro-boxes for Strix HALO and the hand helds are a sign of where the market is going. They don't have a lot of total volume right now, but there is a good variety of those products available out there. There's also the ever increasing volume of uSFF desktops in corporate as a share of the desktop market. These things are going more and more towards just static, disposable boxes.

What is "big APU" here ?

1. Medusa Halo (AT3)
2. Medusa Premium (AT4)
3. Medusa Point 1
4. Medusa Point 2 "little"
5. Medusa Point 3 "baby/bumblebee"

 

[StefanR5R]

@LightningZ71, true; these are good points. If the simplifications which you point out _and_ volume come together, then my argument about mainboard cost (or mainboard price) becomes invalid.

 

[OneEng2]

My 9755 has twice the cores as most of my Zen 4 boxes, and while 500w seems like a lot, and the run a little slower than Zen 5, the compute my GHZ is more. 128 cores at 3 ghz vs 64 cores @ 3.5, I will take the 9755 over 9554. (500 vs 400w the 500 is better used for twice the cores)

Point being that more cores in Zen 6 most likely has the same type of winning power/GHZ.

Most certainly! In addition to getting more cores up to higher speeds at the same power, the server socket for DC Zen 6 is getting a hearty power boost as well! On top of that, more memory bandwidth.

I am thinking Zen 6 is going to be a beast in DC!

 

[adroc_thurston]

I am thinking Zen 6 is going to be a beast in DC

Well yeah but everything since Rome has been a smashmachine.

 

[Markfw]

Well yeah but everything since Rome has been a smashmachine.

speaking as someone who has had every EPYC variation, including Rome and Naples, MIlan.... Genoa is a killer, and Turin is beyond words.

 

[adroc_thurston]

speaking as someone who has had every EPYC variation, including Rome and Naples, MIlan.... Genoa is a killer, and Turin is beyond words.

Venice will be even better.
With a pricetag to match, though.

 

[Kaffeekenan]

Venice will be even better.
With a pricetag to match, though.

Care to elaborate? Because "Venice will be better" should be obvious as hell. The question is how much better.

 

[igor_kavinski]

Care to elaborate? Because "Venice will be better" should be obvious as hell. The question is how much better.

Yeah. Suspicious that we don't have a percent better figure yet. Adroc being cautious?

 

[marees]

Potential medusa apu configurations by olrak (I've added Magnus for reference)

https://twitter.com/x/status/1965106812367299054

 

[SteinFG]

Medusa premium is unlikely to use 3 chiplets. Medusa halo is unlikely to use 4 chiplets. I think this is just too complicated for the laptop segment.

 

[Josh128]

Yeah. Suspicious that we don't have a percent better figure yet. Adroc being cautious?

We do have a percent figure Igor. Its 70%, straight from AMD. Where have you been?


The figure from the slide below is presumably 256 "C" 2nm cores vs 192 "C" 3nm cores. So its at least a baseline to work with. For reference, from Phoronix Geomean testing EPYC gen on gen geomean Linux perf increases are as shown below:

32C 14nm Naples vs 32C 7nm Rome: 39% (34% Blender uplift)
64C 7nm Rome vs 64C 7nm Milan: 15% (3990x vs 5995WX Blender uplift per Techspot is 7%, other sites seem to agree, MT uplift from Rome to Milan was lowest of all gens)
64C 7nm Milan vs 64C 5nm Genoa: 67% ( 46% Blender uplift)
96C 5nm Genoa vs 96C 4nm Turin: ~40% (Blender uplift only 23%, also cant find 64C vs 64C*)
*Found 64C vs 64C 7980X vs 9980X Threadrippers. Blender uplift only 19% per Gamers Nexus

So for the most part, general MT uplift has been much higher for those releases on a full process node advancement. This holds true even for Turin vs Genoa outside of server/enterprise workloads, which seem to be an outlier in that they benefit to a much higher degree from the better Zen 5 arch improvements than "standard" MT workloads such as rendering, compression/decompression, etc. So those workloads aside, Zen 5 vs Zen 4 kind of follows the same pattern as the others-- the largest MT gains come from process node advancements. This means that that Zen 6 will likely carry on that tradition, especially for its 2nm variants.

 

[igor_kavinski]

That's not IPC, though.

More like total platform performance in which the memory subsystem plays heavily too.

 

[Josh128]

That's not IPC, though.

More like total platform performance in which the memory subsystem plays heavily too.

Adroc wasnt speaking about IPC nor was the post he was replying to though. They were merely talking about performance. See my updates above, core for core generational uplifts for each EPYC gen. I still need to add Naples to Rome (32 vs 32) and Im having a bit of trouble with Genoa to Turin (looking for 64 vs 64). **EDIT: Added them.

 

[Josh128]

Hmm...another caveat to consider is that the +70% uplift cited by Lisa and the official slide for Venice is presumably 256"C" 2nm cores vs 192 "C" 3nm cores. This implies that if the 2nm rumors for non "C" core SKUs are true, they will be getting an even larger lithography bump, 4nm to 2nm. If that is true, its quite possible that this +70% figure could be the floor of what is possible.

The MT perf increase from a 16 core 4nm 9950X to a 24 core 2nm flagship could potentially very likely be +85% or more, especially if TDP is raised yet again, say to 200W TDP from 170W. Its very exciting when you consider the possibilities. AMD vs Intel next gen will be fun.

 

[511]

Hmm...another caveat to consider is that the +70% uplift cited by Lisa and the official slide for Venice is presumably 256"C" 2nm cores vs 192 "C" 3nm cores. This implies that if the 2nm rumors for non "C" core SKUs are true, they will be getting an even larger lithography bump, 4nm to 2nm. If that is true, its quite possible that this +70% figure could be the floor of what is possible.

You ain't getting Zen6 with more than 96C on 2nm everything above is 6C

The MT perf increase from a 16 core 4nm 9950X to a 24 core 2nm flagship could potentially very likely be +85% or more, especially if TDP is raised yet again, say to 200W TDP from 170W. Its very exciting when you consider the possibilities. AMD vs Intel next gen will be fun.

Power will be the limit and on client we have Intel 48C which will be even more Power Constrained than Z6 24C.

 

[igor_kavinski]

I'm fully in favor of AM5+ mobos with TDP exceeding 250W. Why should TR and Epyc guys have all the fun?

 

[Abwx]

The MT perf increase from a 16 core 4nm 9950X to a 24 core 2nm flagship could potentially very likely be +85% or more, especially if TDP is raised yet again, say to 200W TDP from 170W.

The 9950X has a 200W PPT, Zen 6 could be 230W PPT at most like Zen 4 since that s the maximum stock power for AM5, so there s not much to gain from a forcibly limited power, the improvement should be something like 75-80% assuming 11% better MT IPC and considering that 2nm will cut power by 40-45%.

 

[511]

The 9950X has a 200W PPT, Zen 6 could be 230W PPT at most like Zen 4 since that s the maximum stock power for AM5, so there s not much to gain from a forcibly limited power, the improvement should be something like 75-80% assuming 11% better MT IPC and considering that 2nm will cut power by 40-45%.

50% more cores to Power as well it's not the same core count. This will be the last huge Shrink AMD or any company will get for that matter. I expect 1.6-1.7X MT in embarrassingly parallel workloads.

 

[Josh128]

You ain't getting Zen6 with more than 96C on 2nm everything above is 6C

Power will be the limit and on client we have Intel 48C which will be even more Power Constrained than Z6 24C.

?? What are you talking about? We already have 128 P cores on 4nm, why would it drop back down to 96 on 2nm?? In any case, I didnt say anything at all about max number of P cores on 2nm, not sure why you are bringing it up as if I did.

EPYC 9755, 128 Zen 5 cores

 

[511]

?? What are you talking about? We already have 128 P cores on 4nm, why would it drop back down to 96 on 2nm??

Ask AMD lol that's what's in roadmap @Kepler_L2 can confirm

 

[Josh128]

50% more cores to Power as well it's not the same core count. This will be the last huge Shrink AMD or any company will get for that matter. I expect 1.6-1.7X MT in embarrassingly parallel workloads.

Its going to be more than 1.7x for 24C 2nm vs 16C 4nm in workloads that scale really well, guaranteed.