Cheesecake16
Member
- Aug 5, 2020
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Why?Since Zen 6 is not a major ground up design from Zen 5 (just a tweak), I see no way SMT will be more effective.
Considering the amount of changes that happened with Zen 5, there are likely some pretty trivial performance gains that could be had... one big one is that fast/slow pathing hazard with the VEC INT which makes all SIMD instructions a minimum of 2 cycles instead of 1 cycle... Another one is the front end effectively being unable to use both decode clusters without SMT...
These are behaviors that are likely to be fixed/improved in Zen 6...
Then what makes you so sure it's "just a tweak" of Zen 5... Zen 2 wasn't "just a tweak" of Zen 1, Zen 3 wasn't "just a tweak" of Zen2, Zen 4 wasn't "just a tweak" of Zen 3, and Zen 5 certainly wasn't "just a tweak" of Zen 4... the 2 cores that were the most similar was Zen 3 and Zen 4 but...:
1) While it's very clear that Zen 4 is derived off of Zen 3, that in no way makes it a simple "tweak"... Adding an ISA as all encompassing as AVX512 is no easy feat and on top of that AMD improved the branch predictor, made the op cache massive and capable of feeding even more instructions to the back end, made the vector register file 512b natively, doubled the L2 cache size, etc.
2) AMD still got fairly impressive performance gains for what was not a complete redesign of the core which is not always needed every generation...