Question Zen 6 Speculation Thread

[Josh128]

1:1 8000 is something to talk about. 1:2 8000 we already have and is an absolute nothingburger.

 

[OneEng2]

Zen 6 is rumored to bring 6400 MT/s compared to 5600 MT/s.

DDR5-8000 is the official support

This is what I understand as well.... and it really is needed to feed 24c/48t Zen 6 IMO.

I don’t know how much they can lower the main memory latency when the IF latency is already 6.5 nanoseconds at 2000 MHz FCLK. If anything, with larger caches and Gear 2 likely being required for client DDR5-8000 support, I’m expecting an increase in system memory latency. Fancy $$$ packaging on client is good for 1. Power 2. Bandwidth 3. Latency in that order, and we already know the new fabric is 32B R/W bandwidth, and it may not be widened, so just expect power to go down.

This would be a good reason to believe the rumors of double stacked 3D cache as this would lower the overall system memory access latency.

 

[adroc_thurston]

to believe the rumors of double stacked 3D cache as this would lower the overall system memory access latency.

It's not gonna do anything.

 

[Joe NYC]

If Intel is in the rearview mirror with AMD's Zen 6 on N3P and single stacked X3D, then it is unlikely AMD will spend the cash on COGS when they can just pocket the profit.

Are you back to inventing CPUs that are not on any leaked roadmap?

There are no desktop CPUs on N3P, only, potentially, monolithic mobile CPUs and those don't have V-Cache.

Maybe they should, but that's a completely different discussion. It will not be a case of holding back "just to pocket the profit", as you suggest, but looking for ways to penetrate Intel's hold on mobile market.

AMD is still an underdog in mobile.

 

[igor_kavinski]

I suggest not even thinking about the latencuck wank and sticking to idk, a 9900k.

The latency issue can be solved by putting high speed RAM (minimum 8GB for cheaper and 16GB for Ryzen 9 series) alongside the CPU. You just need to get your engineer friends to co-operate. You know, the ones you hang out with and enjoy laughing at peasants with.

 

[MS_AT]

DDR5-8000 is the official support

Desktop or Server?

and we already know the new fabric is 32B R/W bandwidth

So the idea is, they will keep the extended interface from Halo? (It's extended in the sense that versus desktop SKUs, Halo has wider write). That will keep the status quo for single and dual CCD SKUs, since their read bandwidth will remain unaffected, and reads are generally done more often than writes, a pity.

 

[adroc_thurston]

The latency issue can be solved by putting high speed RAM (minimum 8GB for cheaper and 16GB for Ryzen 9 series) alongside the CPU

It's DRAM.
It's gonna have DRAM latencies.

You just need to get your engineer friends to co-operate. You know, the ones you hang out with and enjoy laughing at peasants with.

You need to accept the existence that is 100ns+ main DRAM path complex fabric.

 

[igor_kavinski]

You need to accept the existence that is 100ns+ main DRAM path complex fabric.

When Intel figures this chiplet stuff out, their DRAM latency will be sub-70 ns and then AMD will wake up. AMD always has to FOLLOW someone.

 

[511]

DDR5-8000 is the official support

Expected same as server new boards required I guess for this or old board will work fine?

 

[DrMrLordX]

How the hell are you asking this question

The process may have involved a keyboard, and perhaps a monitor as well.

 

[inquiss]

When Intel figures this chiplet stuff out, their DRAM latency will be sub-70 ns and then AMD will wake up. AMD always has to FOLLOW someone.

Why do you think that? What is that based on, anything?

 

[igor_kavinski]

Why do you think that? What is that based on, anything?

Because usually Intel puts more work in for RAM speeds. My XMP 8200 kit just works on my 245KF. But the max I could get it to work at with my 9950X3D was 7200 MT/s. It's only with Arrow Lake's chiplet strategy tragedy that Intel's RAM latency has suffered. Before that, they used to have the lowest RAM latencies.

 

[inquiss]

Because usually Intel puts more work in for RAM speeds. My XMP 8200 kit just works on my 245KF. But the max I could get it to work at with my 9950X3D was 7200 MT/s. It's only with Arrow Lake's chiplet strategy tragedy that Intel's RAM latency has suffered. Before that, they used to have the lowest RAM latencies.

Right. I can see it might go down a bit from what they have, but what I don't get is where your 70ns comes from. That's significantly better than AMD, who are clearly better at interconnecting those chiplets together...

 

[511]

Right. I can see it might go down a bit from what they have, but what I don't get is where your 70ns comes from. That's significantly better than AMD, who are clearly better at interconnecting those chiplets together...

no? Foveros is far superior to the cheap IFOP it's thier clocks and the bad fabric design that is causing this issue on Intel

 

[igor_kavinski]

but what I don't get is where your 70ns comes from.

I'm assuming that they will attack the problem from a fresh perspective. Of course, my assumption goes out the window if their engineers simply give up and accept high RAM latencies as a fact of life.

 

[OneEng2]

Are you back to inventing CPUs that are not on any leaked roadmap?

There are no desktop CPUs on N3P, only, potentially, monolithic mobile CPUs and those don't have V-Cache.

Maybe they should, but that's a completely different discussion. It will not be a case of holding back "just to pocket the profit", as you suggest, but looking for ways to penetrate Intel's hold on mobile market.

AMD is still an underdog in mobile.

I am "speculating" in a thread specifically opened up for "speculation".

Are you seriously debating my speculation with leaks? That seems .... kinda hypocritical doesn't it?

Yea, AMD is still an underdog in mobile AND Lunar Lake is actually a pretty decent chip.

I would actually think that if AMD was going to use N2 on anything, it would be mobile where they could make some headway in market share in mobile.

I have a feeling that even a N3P Zen 6 on the desktop would be sufficient to eclipse the best Intel will have within that same time frame. I could be wrong though.

 

[igor_kavinski]

I would actually think that if AMD was going to use N2 on anything,

I'm guessing they will use N2 for their ARM APU and mobile Zen 6 which will use up any quota they had for desktop chips.

 

[Win2012R2]

I would actually think that if AMD was going to use N2 on anything, it would be mobile where they could make some headway in market share in mobile.

They will use it for the most profitable things -
1. MI400 chiplets
2. Zen6 server chiplets
3. Leftovers here

N3E should work nicely in mobile, which requires high volume anyway that N2 unlikely to provide, certainly not at margins needed to pay for new wafers.

 

[marees]

They will use it for the most profitable things -
1. MI400 chiplets
2. Zen6 server chiplets
3. Leftovers here

N3E should work nicely in mobile, which requires high volume anyway that N2 unlikely to provide, certainly not at margins needed to pay for new wafers.

Looking at the escalating chip prices by TSMC, I am not convinced that anything other than zen6c will be 2nm on AMD side

RDNA 5 is confirmed to be 3nm. Probably MI400 also. MI500 that releases in 2027 could be a good candidate for 2nm

I am not sure if there is a business case for big iron zen 6 servers to be on 2nm
Maybe zen6+ Verano could be the 2nm candidate

 

[adroc_thurston]

When Intel figures this chiplet stuff out, their DRAM latency will be sub-70 ns

How would that happen?

Foveros is far superior to the cheap IFOP

It's just a passive 2.5D slab.
Intel interconnect design is poo.

 

[adroc_thurston]

I am not sure if there is a business case for big iron zen 6 servers to be on 2nm
Maybe zen6+ Verano could be the 2nm candidate

Everything Z6 not msnb is N2p.

 

[511]

It's just a passive 2.5D slab.
Intel interconnect design is poo.

like i said above they botched the interconnect on ARL

 

[Kepler_L2]

Expected same as server new boards required I guess for this or old board will work fine?

I think new boards with updated memory layout/topology will be required

 

[Win2012R2]

Looking at the escalating chip prices by TSMC, I am not convinced that anything other than zen6c will be 2nm on AMD side

MI400 will be the most profitable part per sq mm not just because chip price per se, but because AMD will be selling whole systems with it and getting big hefty margins on stuff that isn't N2 silicon related, but it's the silicon that sells the whole thing, so yes they will use N2 on as many MI400s they can sell.

RDNA 5 is confirmed to be 3nm

Well that makes sense because of the target market: unlike CPUs this is large silicon but low margin.

 

[igor_kavinski]

like i said above they botched the interconnect on ARL

Or maybe it was cutting out the Adamantine cache. No doubt one of Pat's most proud achievements. He killed Optane too. That monster.