Question Zen 6 Speculation Thread

[adroc_thurston]

the fact that ram speed and latency still affects gaming performance is a big one

View attachment 128731
Look at this graph from chips and cheese and I think it can become more clear. There is literally 4x more latency from DRAM compared to L3. If AMD can move that blue line over another segment, cache hit-rates will still continue to go up. Maybe games will finally hit diminishing returns (I doubt it), but overall efficiency would still be greater for any task that would have gone to memory.

We're so lucky that clam also does per-workload cache hitrate breakdowns that for some reason you forgot to poast.
Wonder why.

 

[dr1337]

This chart can't be used as proof that games will see an uplift. It all depends on the size of the working set of the particular game. Depending on the exact figure, additional hitrate may not actually compensate for additional latency of a larger L3.

nah, X3D CPUs literally see more performance in games with faster RAM. Decreasing data movement would objectively lead to more performance, especially they can do it without increasing latency.

Maybe it'd only be 5%, but people pay hundreds of dollars on binned ram for gains less than that.

We're so lucky that clam also does per-workload cache hitrate breakdowns that for some reason you forgot to poast.
Wonder why.

you can post them? If theres one thats really relevant you should share because that would actually be helpful instead of talking down to me and being toxic?

idk why you're trying to call me out, I have no agenda here, just discussing the theory. literally not withholding anything

 

[CouncilorIrissa]

nah, X3D CPUs literally see more performance in games with faster RAM.

That's because it reduces latency in the 96MB+ region with no downside in the sub-96MB region.

especially they can do it without increasing latency.

You can't defy physics, engineers aren't magicians. 1-hi V$ already has a 4 cycle penalty. When going from 32MB to 96MB, those 4 cycles are worth the hitrate surplus. When going from 96MB to 160MB, that surplus is smaller, which might render the additional hitrate pointless in a lot of scenarios due to additional latency.

Maybe it'd only be 5%, but people pay hundreds of dollars on binned ram for gains less than that.

5% is optimistic.

you can post them? If theres one thats really relevant you should share because that would actually be helpful instead of talking down to me and being toxic?

Here's an example of lost throughput due to additional cycles of latency. Already present when going from 32 -> 96MB.

 

[dr1337]

When going from 96MB to 160MB, that surplus is smaller, which might render the additional hitrate pointless in a lot of scenarios due to additional latency.

you don't actually know that for sure, and even if its 2 (or 8) more cycles, its still 3.9x less latency than hitting DRAM

Here's an example of lost throughput due to additional cycles of latency. Already present when going from 32 -> 96MB.

Its literally not a debate that not all games get a benefit from more cache. hence why AMD moved the cache to the bottom die to offset the clock regressions.


What even was the actual difference in FPS/GPU load with that ratio of cache hitrate and IPC? Probably near 0. 1.73 to 1.77 might as well be nothing.

 

[CouncilorIrissa]

you don't actually know that for sure, and even if its 2 (or 8) more cycles, its still 3.9x less latency than hitting DRAM

I don't need to. It's up to you to prove that engineers (and bean counters) are wrong and the hypothetical 2-hi x3d actually makes sense.

Its literally not a debate that not all games get a benefit from more cache.

So why ask for an expensive product that isn't a universal improvement even hypothetically and actually a regression in certain cases?

 

[dr1337]

So why ask for an expensive product that isn't a universal improvement even hypothetically and actually a regression in certain cases?

Are you asking me why x3d exists at all? this has literally been the case since 2022 when 5800X3D was launched.

I don't need to. It's up to you to prove that engineers (and bean counters) are wrong and the hypothetical 2-hi x3d actually makes sense.

but you're just inventing numbers the same as I am? literally all of this is hypothetical. AMD has no published data whatsoever on extra high cache stacks.

 

[CouncilorIrissa]

Are you asking me why x3d exists at all? this has literally been the case since 2022 when 5800X3D was launched.

Don't be intentionally dense, I'm asking why we need a 2-hi X3D given there is present evidence of regressions in some games.

but you're just inventing numbers the same as I am? literally all of this is hypothetical. AMD has no published data whatsoever on extra high cache stacks.

Pointing out evidence isn't inventing? You seem to be laser-focused on this idea that all additional cache capacity needs to do is outperform RAM, while flat out ignoring that additional latency can and will cause regressions while because at a certain point diminishing hit rate gains will no longer offset latency penalty.

 

[OneEng2]

you can post them? If theres one thats really relevant you should share because that would actually be helpful instead of talking down to me and being toxic?

idk why you're trying to call me out, I have no agenda here, just discussing the theory. literally not withholding anything

@adroc_thurston only posts quips. It's against his religion to post proof or reason.

Don't be intentionally dense, I'm asking why we need a 2-hi X3D given there is present evidence of regressions in some games.

Fair enough argument.

Counter: If it is so useless, why is AMD doing it? Do they have a stash of extra die space that they needed to get rid of?

My guess is that there are pretty good gains (likely greater than 5%) associated with double stacking L3 or they wouldn't bother doing it at all.

It may well be that the gains are isolated to a certain type of applications or games, but for those applications, AMD will have struck gold.

 

[StefanR5R]

Maybe it'd only be 5%, but people pay hundreds of dollars on binned ram for gains less than that.

This is after they read hardware reviews in which merely bar graphs are presented as a point of comparison, instead of (double) blind tests with human users which show whether or not – or how – the usability of a given software differs on different hardware.

Re X3D vs. X3DD: Let's assume for a second that the increasing latency when going from 1hi to 2hi stack has negligible effect on a certain choice of software titles, not outweighing the increase in cache hit rate. Then the question is...

It may well be that the gains are isolated to a certain type of applications or games, but for those applications, AMD will have struck gold.

...does having a longer bar in a graph mean to have struck gold? Or being able to provide a usability which is impossible to achieve with a 1hi cache stack? — This is a rhetoric question; I know what beliefs are common currently (in computer forums like this one).

If it is so useless, why is AMD doing it?

The post to which you responded to presented a quantitative regression, not a loss of usefulness.

 

[Win2012R2]

N2 shrinks SRAM so at some point (if they deem it economical to use it for L3 slabs OR it is actually necessary to use N2 for that) we might get 48 MB + 128 MB = 176 MB and latencies should stay the same-ish.

That should remove the need for 2-hi malarkey

 

[Josh128]

2-hi isnt happening on client CPUs (anytime soon, at least). End of story. Increasing the number of cores that can address the L3 pool is the way to go, and AMD is doing that by 50% with Zen 6.

This upcoming gen is going to be exciting from a competitive standpoint, I think. No thanks to 18A.

 

[LightningZ71]

Why would they even try to doublestack it right now? They're already increasing the L3 cache in Zen6 on the base CCD from 32 to 48MB. If they keep their current ratios intact, the X3D cache die will expand from 64MB to 96MB, giving a total cache of 144MB. We'll already have a decent enough test of how sensitive current benchmarks are to L3 size comparing the outgoing X3D product to them.