Keep in mind, for AMD, they treat designs like building blocks. The current rumor mill has AMD preparing two mass market chips relevant to this discussion, an N2 CCD for Zen6 and an N3p Zen6 APU for mobile/desktop. They already have a design package for Zen6/c on both nodes, as well as the relevant L2 and L3 cache blocks, CCX connection blocks, etc. Doing a monster console SOC on those nodes with Zen6/c isn't the lift people are making it out to be. That process is already done, they need to just put the lego pieces together and tape it out. Now, yes, I am VASTLY simplifying this, but that's essentially what we're looking at.