Question Zen 6 Speculation Thread

[yottabit]

Only stated 30% for PS3 emulator, no other numbers

I’m not sure what the context was - AVX-512 support being added to RPCS3 definitely resulted in big performance gains. But between Zen 4 and Zen 5 there was very little improvement in RPCS3 (<3%?) despite the latter having double the theoretical AVX-512 throughput , I’m guessing there is only so much code that can be vectorized in that emulator and the bottleneck is elsewhere. Or maybe it was memory bandwidth bound.

 

[Win2012R2]

Link please. I would love to read that!

https://www.reddit.com/r/GamingLeaksAndRumours/comments/1c4m8co/sony_interactive_entertainment_has_taken_down

He made mistake by showing branded slide as proof

I’m guessing there is only so much code that can be vectorized in that emulator and the bottleneck is elsewhere

AVX512 had a few ops that mapped much easier to PS3, which otherwise required a lot of ops to emulate, that's why Zen 5 did not add much extra.

 

[MS_AT]

But between Zen 4 and Zen 5 there was very little improvement in RPCS3 (<3%?) despite the latter having double the theoretical AVX-512 throughput , I’m guessing there is only so much code that can be vectorized in that emulator and the bottleneck is elsewhere. Or maybe it was memory bandwidth bound.

RPCS3 is using mostly 128b AVX512 flavour, as they are using the fancy AVX512 instructions to better emulate Cell instructions iirc. Since Zen4 -> Zen5 focused mostly on 512b throughput improvements, there is no big advantage for Zen5 here.

 

[OneEng2]

This is a super cope. Intel achieved 6.2 GHz off the shelf boost with their ultra tweaked for frequency 10nm process, ultra binned CPUs, then failed to do so on a far superior 3nm node. AMD failed to move the frequency bar from Zen 4 to Zen 5 despite a tweaked node. There are physical and electrical barriers to frequency increases at a certain point-- inductive, capacitive and transistor switching speed barriers. All these have to line up perfectly to reliably increase speeds. Things become exponentially more difficult as speed increases, its not a linear relation.

Ahhh. A voice of reason.

Everyone who thinks in today's cpu reality that increasing clocks while sacrificing power need to recall P4 Tejas.

 

[Jan Olšan]

You're assuming they got that all from process, and none from design or from deciding to use more power in single core loads.

You're also ignoring that Apple was working with a much lower clock rate and much lower core power than AMD. Its much easier to add 10% frequency when you're starting at 3.5 GHz than it is when you're starting at 6.

I would add that the final clock may not reflect the maximum possible. Sometimes the decision can be to settle for less clock to spare some power consumption. So individual speed bump between products may not really be a reliable guide to "how much the process can give". And can't even reliably reveal how much the uarch+node improved, either.

(And of course, it's the same complicated equation mixing effects of node, uarch and business decisions with AMD or Intel. Who may or may not be pushing clocks to the highest barely shippable point more desperately than Apple in particular past generations, but you never know for certain... yeah, it's all complicated as hell, there are no simple answers and so on)

 

[Josh128]

Tom's hardware story on RPCS3 author's own statement about adding AVX-512 and the perf boost it brought...

Thats nothing to do with Zen 5, that came out with Zen 4. Im talking about comparisons between Zen 4 and Zen 5 on that same emulator.

 

[OneEng2]

I would add that the final clock may not reflect the maximum possible. Sometimes the decision can be to settle for less clock to spare some power consumption. So individual speed bump between products may not really be a reliable guide to "how much the process can give". And can't even reliably reveal how much the uarch+node improved, either.

(And of course, it's the same complicated equation mixing effects of node, uarch and business decisions with AMD or Intel. Who may or may not be pushing clocks to the highest barely shippable point more desperately than Apple in particular past generations, but you never know for certain... yeah, it's all complicated as hell, there are no simple answers and so on)

I agree. Even IF AMD is able to reach 7Ghz, they may not choose to push it that high if Nova Lake is not able to compete well. All AMD needs to do is have performance that is a bit better than Intel. It doesn't make them any more money to be 30% better vs 15% better.

In this case, AMD would be much more likely to go for higher yields than higher clock speed.

This is clear from the way Intel behaved with 14K. Since they were behind the performance curve, they pushed the clocks clear up and beyond the point of safety (rather on yield).... and paid the price.

Still, I wouldn't be surprised to see a Zen 6 at 6Ghz. I would be moderately surprised at 6.3Ghz and STUNNED into silence at 7Ghz .

I expect little in core IPC, a bit from the new IOD and faster memory, and a bit from higher clock (not much higher).

Now in the server, I think AMD will use the N2 process and new IOD to dominate. They will increase throughput and core count far beyond Zen 5 where Turin already holds a commanding lead. AMD has stated that Zen 6 design is "Server First". I am not holding out much hope for large ST improvements.

 

[511]

7Ghz is just out of the ballpark and setting up disappointment expect 6-6.4 ish clocks 6+ GHz is guaranteed though

 

[igor_kavinski]

I want 6.9Ghz core at 6.9 Watts

Sure once they start making CPUs with carbon nanotubes.

 

[poke01]

What was Zen5 clock target? Cause they REALLY did a good job there

 

[Kepler_L2]

WCCFKEK now regurgitating this speculation page as rumor for Zen 6 node, lol.

AMD to Rely on TSMC’s N2P Process for Most Zen 6 Products, Lower-End Laptop SKUs Likely to Use N3P

TSMC's N2P process will supercharge AMD's Zen 6 products, as Team Red appears to combine an architectural leap and node advancements.

wccftech.com

It's not speculation

 

[Kepler_L2]

What was Zen5 clock target? Cause they REALLY did a good job there

Zen3 = 5GHz
Zen4/5 = 6GHz
Zen6 = 7GHz

 

[Kaffeekenan]

What was Zen5 clock target? Cause they REALLY did a good job there

You mean from 5,7 GHz (Zen4) to 5,7 GHz? Not such an amazing job...or is my sarcasmdetector broken?

 

[poke01]

It's not speculation

I think most are confused if it’s normal N2 or N2P. Do you think AMD should have specified when they announced Zen6 DC was on N2?

 

[Kepler_L2]

I think most are confused if it’s normal N2 or N2P. Do you think AMD should have specified when they announced Zen6 DC was on N2?

AFAIK in documents they say it's N2P, however it's almost certainly a custom node that doesn't fit exactly in what TSMC describes as N2/N2P/N2X. In some gfx13/RDNA5 stuff I have seen terms like "AMD3NP" for example.

 

[Io Magnesso]

RPCS3 is using mostly 128b AVX512 flavour, as they are using the fancy AVX512 instructions to better emulate Cell instructions iirc. Since Zen4 -> Zen5 focused mostly on 512b throughput improvements, there is no big advantage for Zen5 here.

Besides, the AVX512/10 is not fixed at 512bit width.
AVX512/10 is the most attractive of various new commands and extended operations.
The 512-bit width is not the place to get a special attention.

 

[soresu]

Besides, the AVX512/10 is not fixed at 512bit width

AVX10 no longer has 128 or 256 bit instructions as of a few months back when the latest revision of the standard came out.

 

[soresu]

Phoronix usually spills the beans well enough @Io Magnesso

Intel AVX10 Drops Optional 512-bit: No AVX10 256-bit Only E-Cores In The Future - Phoronix

www.phoronix.com

 

[soresu]

Ah wait no I misread that horribly.

It does have 128 and 256 bit instructions.

It's only that 512 bit instructions aren't optional anymore.

 

[Io Magnesso]

Ah wait no I misread that horribly.

It does have 128 and 256 bit instructions.

It's only that 512 bit instructions aren't optional anymore.

That's right,
It's just a hardware relationship.
AVX512 has a separate VL (Vector Large) command.

 

[Io Magnesso]

That's right,
It's just a hardware relationship.
AVX512 has a separate VL (Vector Large) command.

They did not utilize the 512-bit width of the AVX512, but used commands and operations.
512bit is not the biggest advantage of AVX512

 

[MS_AT]

512bit is not the biggest advantage of AVX512

Indeed. As Zen4 has shown.

But people fixate on 512 bit (heh) part so we have what we have. I mean it can even improve scalar code if the number of architectural registers is a bottleneck

 

[Josh128]

More Zen 6 speculation, because this is a speculation thread and we need more pages. Read on, the shat could get a bit deep. On potential MT uplift:

Zen 1 to Zen 2 was Samsung/GF 14nm to TSMC 7nm. R7 1800X and R7 3800X were 95/105W TDP SKUs, all same number of cores (8). Using Cinebench R15 MT, we get:


R7 1800X: 1617 CB
R7 3800X: 2164 CB
-------------------------------
+34%

Zen 3 to Zen 4 was TSMC 7nm to TSMC 5nm. R7 5900X & R7 7900X were both 105W TDP SKUs, same number of cores (12). Using Cinebench R23 MT, we get:

R7 3900X: 21507 CB
R7 7900X: 28655 CB
-------------------------------
+33%

So two different sets of nodes, 2 sets of like SKUs that had similar claimed IPC uplifts (15% & 13%) yielded a 33.5% MT gain when jumping up one full TSMC node. If we apply that same logic to Zen 6's 2 full node jump and slightly lower leaked IPC target (10%), you get: 1.3 x 1.3 = 1.69 or +69% MT from Zen 5.

Now, we already have an official claim from Lisa Su that Venice gets a 70% uplift from Turin. This is interesting as its very close to the extrapolated figure above. Assuming this +70% is for the new 256 dense core vs the old 192 dense core, its not quite as apples to apples a comparison as my same core count SKU figures above. Further assuming that at least this is at the same TDP or electrical power as the SKU to which it is compared is helpful.

In any case, I would conclude that Zen 6 is at the very least likely going to get a >50% uplift vs same core count SKUs vs Zen 5, and potentially 70% or more in SKUs that get increased core counts, like a 16 core 9950X vs a 24 core 11950X.

 

[CouncilorIrissa]

Zen 3 to Zen 4 was TSMC 7nm to TSMC 5nm. R7 5900X & R7 7900X were both 105W TDP SKUs, same number of cores (12). Using Cinebench R23 MT, we get:

R7 3900X: 21507 CB
R7 7900X: 28655 CB
-------------------------------
+33%

No? Zen 4 bumped up both dual-CCD chips to 230W PPT (170W TDP).

 

[511]

based on the slide the IPC Improvement can be extracted 15% from node and 33% from core count and dividing 1.7/(1.33*1.15) we get is likely 11-12%