Question Zen 6 Speculation Thread

[soresu]

Sun is fusion not fission.

Going waaaay off topic here, but hydrogen bombs are fission/fusion hybrid thermonuclear weapons.

The initial fission reaction acts like a primer to attain the temp/pressure conditions necessary to achieve fusion ignition on the deuterium/tritium fuel.

They are called hydrogen bombs, but in reality they all use the deuterium and tritium isotopes of hydrogen with 1 and 2 neutrons respectively.

Regular zero neutron hydrogen has a greater fusion energy yield than either deuterium, tritium or combinations thereof, but making regular hydrogen fuse takes serious oomph.

 

[Io Magnesso]

Well duh, it has 4 ring-stops and not 12, thrice as small and is in general an entirely different thing.

Well, which way, LUNAR LAKE was ahead of its release, but it seems that the design itself started after ARROW LAKE. At least there will be an improvement

 

[Doug S]

There is no need for a 240MB additional cache in a consumer environment

I think people here jonesing for it are greatly overestimating the amount of benefit. Diminishing economies of scale adding to an already massive cache, plus having three layers (the CPU and two SRAM chips) means heat is a bigger problem - if it dropped your clock rate by even 100 MHz you'd likely end up losing performance.

Pretty sure AMD has tested this internally, and would be considering it at least for server CPUs (where you can get crazy additional upcharge for a very small gain in performance) if it was as big of a win as some people seem to be assuming.

 

[Io Magnesso]

I think people here jonesing for it are greatly overestimating the amount of benefit. Diminishing economies of scale adding to an already massive cache, plus having three layers (the CPU and two SRAM chips) means heat is a bigger problem - if it dropped your clock rate by even 100 MHz you'd likely end up losing performance.

Pretty sure AMD has tested this internally, and would be considering it at least for server CPUs (where you can get crazy additional upcharge for a very small gain in performance) if it was as big of a win as some people seem to be assuming.

That's right, I agree
I think AMD will come out with the appropriate capacity.
The more cash you have, the better it isn't…
The more cash you have, the more difficult it will be to manage…

 

[adroc_thurston]

means heat is a bigger problem

SRAM isn't toasty and cores are on top anyway.
There's just no ROI in even more chunggus L3.

 

[DavidC1]

It was fixed in lunar lake. that one is 52 cycles.

It wasn't fixed in Lunarlake. It's also three stops less than 6+8 Meteorlake since the E cores are LPE cores and aren't on the ring.

Of course Lunarlake can be excused for low power. Arrowlake cannot.

SRAM isn't toasty and cores are on top anyway.

That's right. SRAM is power and area efficient.

There's just no ROI in even more chunggus L3.

Chungus is a cringey, rebellious teenager term.

 

[DrMrLordX]

Big Chungus is a pretty old meme by this point. That aside, unless Intel builds on Lunar Lake's core/cache topology in the future (which it looks like they aren't), it's not likely that Intel's L3 latency will catch up to Zen5 or 6 anytime soon. Stacking a whole bunch more L3 with those latencies and read speeds doesn't look to be a good way to combat Zen6 X3D.

 

[Io Magnesso]

Big Chungus is a pretty old meme by this point. That aside, unless Intel builds on Lunar Lake's core/cache topology in the future (which it looks like they aren't), it's not likely that Intel's L3 latency will catch up to Zen5 or 6 anytime soon. Stacking a whole bunch more L3 with those latencies and read speeds doesn't look to be a good way to combat Zen6 X3D.

I don't know what's going on for desktop, but at least for laptops will improve.

 

[511]

Sun is fusion not fission.

Fusion of Hydrogen creates Helium which is also part of the sun's gaseous composition.
Also just like fusion of two compute tiles creates AMD Desktop CPUs 🙂

 

[itsmydamnation]

this is the only Fusion that matters

 

[Win2012R2]

There is no need for a 240MB additional cache in a consumer environment

Premium top end product, if they make server version then why not get $1k top end SKU, no brainer.

This could be good for APUs too - finally plenty of "infinity cache" to offset slow laptop/desktop RAM.

 

[MS_AT]

This could be good for APUs too - finally plenty of "infinity cache" to offset slow laptop/desktop RAM.

Since you are talking about APUs, I guess you mean IGPU only scenarios, what I guess means you would expect the 240MB X3D cache to help the IGPU itself, but nope, it won't it's CPU only cache.

 

[Win2012R2]

Since you are talking about APUs, I guess you mean IGPU only scenarios, what I guess means you would expect the 240MB X3D cache to help the IGPU itself, but nope, it won't it's CPU only cache.

Why can't it be used for 3D stacked iGPUs? Seems like perfect solution to low mem bandwidth, obviously this needs to be architected into iGPU itself, seems like plenty of time passed since it was first released for CPUs

 

[Io Magnesso]

Since you are talking about APUs, I guess you mean IGPU only scenarios, what I guess means you would expect the 240MB X3D cache to help the IGPU itself, but nope, it won't it's CPU only cache.

I agree
If you're going to do it, you have to make it as a system cache
Also, I don't remember much about the infinity Cache's huge capacity.
Come to think of it, the capacity has decreased from rDNA3 compared to RDNA2.

 

[Io Magnesso]

Why can't it be used for 3D stacked iGPUs? Seems like perfect solution to low mem bandwidth, obviously this needs to be architected into iGPU itself, seems like plenty of time passed since it was first released for CPUs

It's not that V-Cache technology can't be used with Infinity Cache…
It seems that various designs need to be reviewed.

 

[Win2012R2]

It's not that V-Cache technology can't be used with Infinity Cache…

One would have thought that V-cache would work even better with large GPU because it will be right under it - so latencies can be reduced.

AMD's own RDNA2 info shows that even 128 MB gets 80% hit rates in 1080p, 70% for 1440 and 60% in 4K - so doubling that AND having lower latencies due to placement should make APUs perform real well despite slow RAM.

 

[Io Magnesso]

One would have thought that V-cache would work even better with large GPU because it will be right under it - so latencies can be reduced.

AMD's own RDNA2 info shows that even 128 MB gets 80% hit rates in 1080p, 70% for 1440 and 60% in 4K - so doubling that AND having lower latencies due to placement should make APUs perform real well despite slow RAM.

But how do you implement it? There is a problem that
If you want to use 3D-V Cache not only from the CPU but also from other units, you have to think about where to put it.

 

[Win2012R2]

But how do you implement it?

Same way as they did on CPUs (using TSVs) - slab of 3D cache at the bottom of big GPU, which can get bigger because no need to put L3 there - cache can be quicker also as it's closer, maybe it's even easier because you don't have to think of multiple chiplets accessing it via IF.

Considering GPUs are far more tolerant of higher latencies this should work like a charm - leaving more space for logic made on new nodes, maybe it will even cut latencies, plus GPUs are bigger than small CPUs so potentially a LOT more cache can be added: 256 MB should cover 4k scenarios easily.

 

[adroc_thurston]

Considering GPUs are far more tolerant of higher latencies

That was Very True but then RTRT happened.

 

[Io Magnesso]

Same way as they did on CPUs (using TSVs) - slab of 3D cache at the bottom of big GPU, which can get bigger because no need to put L3 there - cache can be quicker also as it's closer, maybe it's even easier because you don't have to think of multiple chiplets accessing it via IF.

Considering GPUs are far more tolerant of higher latencies this should work like a charm - leaving more space for logic made on new nodes, maybe it will even cut latencies, plus GPUs are bigger than small CPUs so potentially a LOT more cache can be added: 256 MB should cover 4k scenarios easily.

If you do that with dgpu, it's still easy to do
The problem is how you implement the APU you mentioned earlier.

 

[Io Magnesso]

That was Very True but then RTRT happened.

rtrt? Ray tracing?

 

[igor_kavinski]

rtrt? Ray tracing?

realtime raytracing

 

[Io Magnesso]

realtime raytracing

I see, thank you eggplant

 

[MS_AT]

Why can't it be used for 3D stacked iGPUs?

We were talking about CPUs when I made the comment, thikining we are talking about cache slab on the cpu ccd. If you fancy you can put the slab on the igpu too and connect it to its caches, in theory it should be possible. Iirc for RDNA3 they were considering 3d cache.

 

[adroc_thurston]

Why can't it be used for 3D stacked iGPUs?

a) cost
b) no one actually uses iGPUs.