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Question Zen 6 Speculation Thread

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OneEng2 said:
All in all, I think that the new IOD and faster memory speeds are going to be the biggest improvements we see in Zen 6 platforms next year.

I am actually not expecting much in the way of IPC of Zen 6 over Zen 5 (10-15%) and little or no increase in clock speed. In more bandwidth limited operations (likely in DC applications / HPC /AI) much larger increases in performance will be seen than the IPC bump. At a minimum, we can expect the larger core counts will result in higher performance. The IPC and bandwidth increases would then be on top of that.

Zen 6 Venice should be a very powerful platform indeed.
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That will be true for ST, but not for MT. Much like Zen 3>Zen4, the process node change should allow for MUCH higher MT all core clocks than current 4nm Zen 5, which actually clocks lower than Zen 4 in all core R23 runs.

So while AMDs own leaked MLID slide claimed +~10% IPC for Zen 6, I think we are looking at significantly increased all core clocks when comparing say, 16 core Zen 6 to 16 core Zen 6 at the same 170W TDP.

So in the end, it seems Zen 6 will reap the the benefits of Zen 2 to Zen 3 (increased size CCX), and Zen 3 to Zen 4 (much higher core for core MT freq).
 
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MS_AT said:
Out of curiosity, at what power limits?
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I think if both are limited to 230W, I think 9950X limits to around 150- 200MHz per core lower compared to 7950X in R23 or R24. I dont know the exact numbers, and it depends on the workload, but its at least a bit lower across the board.

Here at GN its around 100MHz or so lower in the Blender test.
1750099227745.png
 
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Josh128 said:
I think if both are limited to 230W, I think 9950X limits to around 150- 200MHz per core lower compared to 7950X. I dont know the exact numbers, but its lower.
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That's the thing that gets people tripped up with Granite Ridge: the PPT no longer follows the 1.35*TDP "rule". The 9950X PPT is 200w. Hence the ~100 MHz lower clock speeds.
1750099107235.png
edit: removed the wrong ppt image
Later in the same video you can see the ~30w delta measured between 7950x and 9950x
1750099654986.png
 
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OneEng2 said:
Absolutely. Of course, for many of the benchmarks being quoted, the transfers are artificially large in order to explicitly ensure that it will come from main memory.

In real world applications, I think that this is rarely the case and quite a bit of memory access is kept local within one of the levels of cache thus preventing a main memory access. Additionally, the specific memory elements in cache are frequently accessed repetitively.

All in all, I think that the new IOD and faster memory speeds are going to be the biggest improvements we see in Zen 6 platforms next year.

I am actually not expecting much in the way of IPC of Zen 6 over Zen 5 (10-15%) and little or no increase in clock speed. In more bandwidth limited operations (likely in DC applications / HPC /AI) much larger increases in performance will be seen than the IPC bump. At a minimum, we can expect the larger core counts will result in higher performance. The IPC and bandwidth increases would then be on top of that.

Zen 6 Venice should be a very powerful platform indeed.
Click to expand...
The biggest improvement for desktop Zen6 over Zen 5 will be the foundry node. Going from N4P to N2P is a big jump in area inside the node triangle (efficiency, performance, density). This should lead to considerably gains in efficiency with respect to watts consumed at a given clock frequency over time. That typically translates to a big jump in MT performance due to higher sustained clocks across all active cores. So long as they aren't memory bandwidth bound, MT tasks should improve well.
 
LightningZ71 said:
The biggest improvement for desktop Zen6 over Zen 5 will be the foundry node. Going from N4P to N2P is a big jump in area inside the node triangle (efficiency, performance, density). This should lead to considerably gains in efficiency with respect to watts consumed at a given clock frequency over time. That typically translates to a big jump in MT performance due to higher sustained clocks across all active cores. So long as they aren't memory bandwidth bound, MT tasks should improve well.
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Are there any credible sources claiming that it will use N2P for desktop? I think its more possible that desktop could use N3P or N3X?
 
N3X for a product that will likely see mobile duty doesn't make sense. Talking about the CCDs, N2/P makes the most sense. The IOD and the successor to Kraken will likely be on an N3 family node. Rumor has it that Kraken is provisioned to connect a CCD, which will likely be on N2/P.
 
Josh128 said:
Are there any credible sources claiming that it will use N2P for desktop? I think its more possible that desktop could use N3P or N3X?
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I agree; however, I think you will find that the vast majority of forum members believe it will be N2.

I think that AMD could keep to near their current die size and go to a 12 core CCD just by moving from N4P to N3P.

To answer your question directly, I don't believe there is any proof or statements from AMD that conclude that the desktop Zen 6 will be on N2.
 
CakeMonster said:
MS themselves counted on it being Z6 based when the FTC docs leaked a few years back, so I'm giving it 95% of being a Z6 derivative.
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I wonder if it is going to be chiplet based...

Something along the lines of LPDDR6 Medusa Halo might be ideal for consoles, but the cost may be too high...
 
Yeah I have tons of questions (and worries) about the platform, like RT and AI capability and VRAM capacity, that will actually be more interesting than the CPU architecture IMO which would have been more or less current anyhow. Though number of CPU cores is actually interesting, I hope at least for future headroom they will move past 8c/16t. The next gen will probably last until 2034 at a minimum. Having experienced late gen ridiculous bottlenecks with most of the previous gens (which do also impact PC releases) I'm kind of neurotic about this stuff now 😛
 
So the PlayStation handheld likely to be 4x zen 6 p-cores


marees said:
Details of PS5 low power mode as leaked by MLID

Here are the specs revealed about the PlayStation 5 Low Power Mode (according to the leak):

  • Limits CPU usage to 8 threads
  • Cuts 3D audio processing power to 75%
  • Clocks down GDDR6 memory to half speed
  • Reduces core (CPU/GPU) clocks by about 10–20%
  • Sets GPU to the minimum frequency needed for compatibility
  • Limits the console to 36 Compute Units
  • No PSSR (PlayStation Spectral Super Resolution), or VR support in this mode

thegamepost.com

PlayStation 5 Leak Reveals New 'Low Power' Mode, Fueling Handheld Console Reports

A new leak suggests Sony is rolling out a "low power" mode for the PlayStation 5 and PlayStation 5 Pro to developers, with ongoing rumors about a PlayStation handheld console in the works
thegamepost.com thegamepost.com
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