Question Zen 6 Speculation Thread

[CakeMonster]

15% will be decent considering recent developments...

Timing is going to be interesting though... cycles have been getting longer.

 

[DavidC1]

Because you're literally like a year away from aa64 camp putting out 5Ghz chips.

Which comes from natural process enhancements. The rest of the performance is due to efficient uarch design not prioritizing on clocks like the x86 camp.

Saying AMD/Intel is falling behind because of the x86 ISA is a convenient excuse for how badly both are doing, since it's just a self-fulfilling prophecy - the only difference is one is mediocre and the other is falling flat on it's face every year.

(Ok to AMD's credit I would say better execution with misguided ideas, versus Intel which is worse execution with the same misguided ideas)

 

[adroc_thurston]

Which comes from natural process enhancements

No it comes from opting for performance cells and relaxing the metal stack.

The rest of the performance is due to efficient uarch design not prioritizing on clocks like the x86 camp.

Yes they in fact do prioritize clocks. Next.

Saying AMD/Intel is falling behind because of the x86 ISA is a convenient excuse for how badly both are doing, since it's just a self-fulfilling prophecy - the only difference is one is mediocre and the other is falling flat on it's face every year.

?

 

[DavidC1]

Because you're literally like a year away from aa64 camp putting out 5Ghz chips.

How are you justifying 20% clock difference with 2x pipeline stage difference?

20 years ago it made sense, because 2x pipeline resulted in near 2x gains. So if it was 20 years ago, Apple would have been struggling to put out 3GHz chips. Instead, they are near 5GHz.

The fact that there's a 3-4x power difference with a generational single thread advantage is an indicator that the x86 vendors are on a wrong road - they just happen to be swerving between the lanes. No, they need a complete departure like P4 vs PM.

 

[adroc_thurston]

How are you justifying 20% clock difference with 2x pipeline stage difference?

2x?
The delta between Apple and AMD cores is like 6 stages.
Only ARM cores are shallow (10 stages) but they also clock like crap.

The fact that there's a 3-4x power difference with a generational single thread advantage is an indicator that the x86 vendors are on a wrong road - they just happen to be swerving between the lanes

Put Zen5 on N3e 3-2 and watch pigs fly.

 

[Hulk]

I don't think frequency is going to be going up unless there is some breakthrough in terms of either transistor heat generated or cooling solutions.

Zen 5 can run up to 5.7GHz on 2 cores and then it ramps down from there as more cores are loaded. The issue isn't so much there are only 2 "good" core that can do the frequency, but the fact that we are trying to dissipate 200+ Watts out of a very small area. Either you spread out the "hot" surface, which is unlikely, decrease the heat generated at high frequencies, which is also very difficult, or increase the heat transfer between the CPU and the cooling solution. Generally that means direct-to-die or sub ambient cooling.

If you look at both ARL and Zen 5, they are both frequency limited by heat, not the process or architecture per se.

Some innovative redesign of the heat spreader/TIM would be a good start on increasing frequencies for higher core counts. We are simply hitting a heat transfer barrier with the enormous heat flux all of these tiny transistors are creating.

 

[eek2121]

I don't think frequency is going to be going up unless there is some breakthrough in terms of either transistor heat generated or cooling solutions.

Zen 5 can run up to 5.7GHz on 2 cores and then it ramps down from there as more cores are loaded. The issue isn't so much there are only 2 "good" core that can do the frequency, but the fact that we are trying to dissipate 200+ Watts out of a very small area. Either you spread out the "hot" surface, which is unlikely, decrease the heat generated at high frequencies, which is also very difficult, or increase the heat transfer between the CPU and the cooling solution. Generally that means direct-to-die or sub ambient cooling.

If you look at both ARL and Zen 5, they are both frequency limited by heat, not the process or architecture per se.

Some innovative redesign of the heat spreader/TIM would be a good start on increasing frequencies for higher core counts. We are simply hitting a heat transfer barrier with the enormous heat flux all of these tiny transistors are creating.

Funny you mention the 5 GHz thing. The latest bet a ASUS bios for my board (with 7950X) had 4 (!!!) cores hitting 5.7 ghz with the CCD parking for games enabled. It bounced around due to thermals. Perhaps the 9950X may need to be revisited.

Who knows what Zen 6 will bring?

 

[adroc_thurston]

If you look at both ARL and Zen 5, they are both frequency limited by heat, not the process or architecture per se.

'heat' is a function of your process node lmao.

 

[Jan Olšan]

Whole lot more than that.
Going to N2p nets them like 20% speed with nano-flex usage.

The clock increases quoted for process nodes are never talking about maximum clocks, so don't expect them to translate into processor products' maximum rated boost clocks this time either.

 

[adroc_thurston]

The clock increases quoted for process nodes are never talking about maximum clocks

That's why fabs provide freq plots for new nodes besides just blanket statements. There's one for N2 too.

 

[Jan Olšan]

Well, if Zen 6 knocks me off the chair with 15% boost clock bump (6.6 GHz?), I'll be... extremely pleasantly surprised. Unless it melts power connectors or something.

Now I gotta hope they won't do another Zen4-like repipelining/architectural speeddemonizing this time, which would make it look like my prediction failed and yours was bullseye

 

[inquiss]

Yea, and the TDP went up from 105W to 170W despite moving to a new process. Pretty sure that has nothing to do with significant clock increase. If they can get significantly above 6GHz(which I have doubts), then they can have their own Raptorlake.

Who cares about that TDP in desktop. No one.

 

[Thunder 57]

Who cares about that TDP in desktop. No one.

Me. Living in a warm part of the country that matters. Not as much with CPU's, but definitely GPU's.

 

[adroc_thurston]

Well, if Zen 6 knocks me off the chair with 15% boost clock bump (6.6 GHz?), I'll be... extremely pleasantly surprised

It's completely normal.
Zen4 was also a 15% ish fmax bump on DT, and that was a single node shrink. Not two.

Now I gotta hope they won't do another Zen4-like repipelining/architectural speeddemonizing this time

Zen4 wasn't repepipelined at all? It was a completely by the numbers Zen3 derivative.

 

[gdansk]

Zen 6 doesn't have much going for it if you thought Zen 4 was disappointing.

It's a Zen 4 tier IPC increase. But without a Zen 4 tier clock increase? So we better hope it clocks higher.

And for gamers I'm not sure the 12 core CCD will be an improvement for most games as core-to-core latency will be stable or possibly worse.

 

[adroc_thurston]

And for gamers I'm not sure the 12 core CCD will be an improvement for most games as core-to-core latency will be stable or possibly worse.

you literally get 50% moar L3.

 

[gdansk]

you literally get 50% moar L3.

It may help the base models. But that's not what gamers are buying.
Anyone who thinks Zen 6 can be good without a clock rate increase will be disappointed. It needs a higher clock rate.

 

[adroc_thurston]

But that's not what gamers are buying.

V$ also gets to be 50% (or whatever) bigger, since your SRAM macro extends with the slice count.

Anyone who thinks Zen 6 can be good without a clock rate increase will be disappointed

Well no future core on the market will be good without an fmax bump. Which is what everyone is doing anyway.
Crank 'em up boyz

 

[gdansk]

Well no future core on the market will be good without an fmax bump. Which is what everyone is doing anyway.

Some more than others.
Apple needs a whopping 0% clock increase to be ahead of Zen 6 at 5.7GHz. So those on AM5 better face the music and realize Zen 6 needs a clock rate increase. The other option is AMD under hyping and over delivering (and they haven't done that in half a decade).

 

[adroc_thurston]

Some more than others.

Uh, nope.
It's kinda the issue for x86 in mobile, paltry 6% fmax gain in 4 years.
Medusa premium will shift the paradigm for AMD at least, what's with the full cache CCD n all.

Apple needs a whopping 0% clock increase to be ahead of Zen 6 at 5.7GHz

They're also out of options wrt core bloat. Too bad!

 

[poke01]

Some more than others.
Apple needs a whopping 0% clock increase to be ahead of Zen 6 at 5.7GHz. So those on AM5 better face the music and realize Zen 6 needs a clock rate increase. The other option is AMD under hyping and over delivering (and they haven't done that in half a decade).

Apple hasn't even been designing desktop CPUs. Only for laptops.

STX halo tops out at 5.1GHz, this year Apple will get closer to x86 laptop cpu clocks than ever before.

 

[poke01]

They're also out of options wrt core bloat. Too bad!

ehh, they can add smt for MT gains

 

[adroc_thurston]

ehh, they can add smt for MT gains

a) never
b) never^2 since validating SMT on yearly cadence is asking for trouble

 

[gdansk]

Apple hasn't even been designing desktop CPUs. Only for laptops.

It doesn't matter. The point is that AMD needs to increase clock rates with Zen 6. The characteristics of the Zen 6 core are not sufficient except with a clock rate increase.

 

[jpiniero]

ehh, they can add smt for MT gains

What, no SMT4?