Question Zen 6 Speculation Thread

[adroc_thurston]

I don't think I'll be able to afford those server chips, not with memory prices as they are, so this time thinking about personal Zen6 upgrade.

No, I mean you can model clock/nT IPC improvement going off the provided Venice data already.
Mind that this time dense to dense comparison carries a doubled LLC per core.

 

[Joe NYC]

As much as I like the idea you are most likely right, from what I could see AMD sold a lot of Milan-X to companies that got high per core licensing costs and 3D cache was big speed up for the software that was used (like EDA), so those favour fast clocked cores + lots of cache, where as max core SKUs are for hyperscalers that run independent workloads on them.

Genoa-X as well.

 

[inquiss]

That's too generic, what I'd like to know single thread perf, clock rates (especially all cores) - plus of course Zen6X3D stuff, they'd better release it from start without delay.

The delay is how long it takes to add the 3D cache. It can't come out a the same time unless you delay the launch of zen 6 itself

 

[adroc_thurston]

The delay is how long it takes to add the 3D cache. It can't come out a the same time unless you delay the launch of zen 6 itself

Ah no they can launch it day 0.

 

[inquiss]

Ah no they can launch it day 0.

How so? Chips come out, they then need to have cache hybrid bonded. That takes time. So they can launch day 0 only if they delay the launch of non stacked chips.

 

[adroc_thurston]

How so? Chips come out, they then need to have cache hybrid bonded. That takes time. So they can launch day 0 only if they delay the launch of non stacked chips.

Uh, no, SoIC process flow ain't *that* long.

 

[reaperrr3]

Uh, no, SoIC process flow ain't *that* long.

There's also that by the time a new generation launches, AMD has been producing them for months, the launch volume will consist of several batches that have been accumulated over a longer timeframe to build up volume while production is ramping.
So for X3D, it's more the question of how aggressively the CCDs are binned (are only 3% of dies per wafer good enough for the top X3D SKU specs?) and how much volume AMD want to have ready for a launch.
...And how much vanilla model volume they want to sell at MSRP to impatient DIYers first.

 

[cherullo]

Those you can model off Venice perf numbers.
They're SIR2017 n-copy so remember the scaling rate.

If I remember correctly you tried this with Zen5 and it didn't map well to client workloads.

 

[StefanR5R]

If I remember correctly

No, that was about "IPC", while this is about clock speeds.

 

[Makaveli]

CES 2026: Taking the Lids off AMD's Venice and MI400 SoCs

Here at CES 2026, AMD showed off their upcoming Venice series of server CPUs and their upcoming MI400 series of datacenter accelerators.

chipsandcheese.com

 

[CakeMonster]

Have we done a poll of what people think will be Zen6 and Zen63D release dates? Could be fun to see who gets it right.

 

[Joe NYC]

Have we done a poll of what people think will be Zen6 and Zen63D release dates? Could be fun to see who gets it right.

Don't know when, but I think it is very likely that:

Zen6 release date = Zen63D release date

 

[adroc_thurston]

Zen6 release date = Zen63D release date

They'll probably time the V$ parts to intercept NVL-S.

 

[Fjodor2001]

They'll probably time the V$ parts to intercept NVL-S.

Yeah, likely if they can. But they do not know the release date of the NVL-S SKUs with bLLC. So are you suggesting AMD will produce Zen6 X3D SKUs and hold them in storage until those NVL-S SKUs released? That is of course assuming those Zen6 SKUs actually will be ready before the NVL-S ones.

 

[adroc_thurston]

But they do not know the release date of the NVL-S SKUs with bLLC

Of course they do.

So are you suggesting AMD will produce Zen6 X3D SKUs and hold them in storage until those NVL-S SKUs released?

Yeah.

That is of course assuming those Zen6 SKUs actually will be ready before the NVL-S ones.

Well AMD post-Si teams are not lobotomized.

 

[Joe NYC]

They'll probably time the V$ parts to intercept NVL-S.

Do you mean split launch or holding back the non-V-Cache launch?

 

[adroc_thurston]

Do you mean split launch or holding back the non-V-Cache launch?

The former, it's the normal AMD cadence.
AMD doesn't have to "hold back" anything, they own the place.

 

[Fjodor2001]

Of course they do.

By what mechanism you mean? Industrial espionage, industry rumors, …?

 

[Joe NYC]

The former, it's the normal AMD cadence.
AMD doesn't have to "hold back" anything, they own the place.

Yeah, that's the standard procedure, but with such an overwhelming success of the V-Cache parts, I am not sure if AMD ends up changing their pattern of introductions.

 

[Joe NYC]

By what mechanism you mean? Industrial espionage, industry rumors, …?

Both companies have to sell to, and bid against each other with their OEM customers.

 

[adroc_thurston]

By what mechanism you mean? Industrial espionage, industry rumors, …?

You do understand that both vendors share platform/product roadmaps with launch quarters and stuff?

but with such an overwhelming success of the V-Cache parts, I am not sure if AMD ends up changing their pattern of introductions.

You always double dip.

 

[Joe NYC]

You always double dip.

Doing so is a little bit of a gimmick.

We will see how AMD adjusts to their newly found success. Maybe they no longer have to use gimmicks.

 

[adroc_thurston]

Doing so is a little bit of a gimmick.

it's a normal market strategy

 

[Fjodor2001]

Both companies have to sell to, and bid against each other with their OEM customers.

OEMs might release different PC model variants with different CPUs at different dates. E.g. if Zen6 X3D is ready 3-6 months before NVL-S bLLC (or vice versa), the OEMs will not hold back and release both PC model variants at the same time.

So just because AMD know when the OEM intends to release models with its CPUs does not mean they know when that OEM intends to release models with a specific competitor CPU.

You do understand that both vendors share platform/product roadmaps with launch quarters and stuff?

Share with whom? Also, launch quarter or half-year is a quite wide window. Anything from 3-6 months difference if at beginning or end. On top of that, things may get delayed anyway.

 

[adroc_thurston]

Share with whom?

A whole lot of employees.

Also, launch quarter or half-year is a quite wide window

No it's not.
Q2'27 means Computex launch.
Q1'27 usually means CES launch. There are events or indicative market cycles (like b2s or holiday seasons) to track launches.

On top of that, things may get delayed anyway.

Yes I know Intel sucks. You don't have to say that for me.

the OEMs will not hold back and release both PC models at the same time.

They do what AMD tells them to do.
They can't do stuff till it's GA, and AMD says when GA is and how and why.