Question Zen 6 Speculation Thread

[Doug S]

with direct interfaceless copper-to-copper bond.

So because technological advances have removed most of the penalty for die crossing it no longer counts as a separate die?

 

[adroc_thurston]

So because technological advances have removed most of the penalty for die crossing it no longer counts as a separate die?

It just lacks performance limitations associated with offdie caches, so kinda?

 

[OneEng2]

If you are already in the chart please provide the rest of your prediction data. Moving forward I'm only going to enter data if all data in red font is submitted so the chart is complete.

View attachment 132961

Hi Hulk.

Put me down for 24c, 200W, 4.5Ghz, 67000.

I think that AMD will not go beyond the 200W (or they would have done it with Z5). I think they will get better performance in CB running more cores at a lower clock and that the new IOD will provide uplift beyond the core on this benchmark.

 

[gdansk]

AMD will not go beyond the 200W (or they would have done it with Z5).

They did with Zen 4...

 

[Abwx]

If you are already in the chart please provide the rest of your prediction data. Moving forward I'm only going to enter data if all data in red font is submitted so the chart is complete.

View attachment 132961

I used your 9950X score as basis with 11% IPC uplift, that make about 4.83GHz@200W and 5.04GHz@230W.

 

[Hulk]

 

[OneEng2]

They did with Zen 4...

True that!

I suspect that Intel will not push AMD that much (just suspect). If this is true, AMD will push for high yields and low fall out in the field to maximize profit IMO.

But should NVL be a big winner and surprise me, you may well be correct and we will see AMD push Zen 6 to ~ 220W.

Right now, I'm guessing 200W .

 

[OneEng2]

View attachment 132984

I feel like an outlier when you put it in context .

I am guessing in this particular benchmark that the IOD is going to move the needle .... maybe more than the core enhancements.

Let's see if I am right! You have it captured now so I can't pretend I didn't say it

 

[Fjodor2001]

True that!

I suspect that Intel will not push AMD that much (just suspect). If this is true, AMD will push for high yields and low fall out in the field to maximize profit IMO.

But should NVL be a big winner and surprise me, you may well be correct and we will see AMD push Zen 6 to ~ 220W.

Right now, I'm guessing 200W .

I’m not so fond of these high 200/230W numbers. I guess it’s to squeeze out the last bit of perf to win some benchmark crown.

I’m hoping that it’ll perform good in perf/watt if not the pushing power consumption that high. E.g. for 9950X you could limit TDP from 170W to ~105W without losing much MT perf. I wonder what the TDP sweet spot will be for 24C Zen6.

 

[511]

No, Intel L2 is like 19 cycles and runs cclk.

It's 4MB L2 on Skymont reduced to 17 cycles in darkmont AMD L2 Is 13-14 Cycle for 1MB.

 

[lixlax]

View attachment 132984

I'll join in as well for the fun.
24c, 200W, avg freq. ~4,8GHz, score ~66500p. That should be a conservative IPC increase of ~5-6% (for Cinebench), average application IPC will be a little bit higher. With gaming it will inflate over 10% which AMD will use for marketing. I expect the all core clockspeed to be similar to 9950X due to 50% more cores eating up most of the the power savings from better node.
In case of 230W I'd say ~5,1GHz and ~70000p.
By modern standards it should be a fairly good overclocker (close to 80000p with custom water and direct die). Stock vs stock Intels 48c to end up 5-10% faster in Cinebench.

 

[Hulk]

 

[adroc_thurston]

It's 4MB L2 on Skymont reduced to 17 cycles in darkmont AMD L2 Is 13-14 Cycle for 1MB.

Oh idgaf about Atoms.
I mean Intel's actual big cores.
They have like an 18c 3M L2 slab.
Pretty good!

 

[511]

L3 Latency though almost 2X of AMD ...

 

[AMDK11]

https://substackcdn.com/image/fetch/$s_!udpZ!,w_1456,c_limit,f_webp,q_auto:good,fl_progressive:steep/https%3A%2F%2Fsubstack-post-media.s3.amazonaws.com%2Fpublic%2Fimages%2Fb2a214eb-2da5-4c87-99b0-8279d5c9e4e5_1034x584.png

Examining Intel's Arrow Lake, at the System Level

Arrow Lake is the codename for Intel's newest generation of high performance desktop CPUs.

chipsandcheese.com

 

[Josh128]

I’m not so fond of these high 200/230W numbers. I guess it’s to squeeze out the last bit of perf to win some benchmark crown.

I’m hoping that it’ll perform good in perf/watt if not the pushing power consumption that high. E.g. for 9950X you could limit TDP from 170W to ~105W without losing much MT perf. I wonder what the TDP sweet spot will be for 24C Zen6.

Me neither, but the "sweet spot"for 24 SMT2 cores that are supposedly able to reach 6GHz + handily is going to be HIGH. While the perf increase from Zen 4 and especially Zen 5 from 200W to 230W is not at all worth the extra 15% power consumption, that will NOT be the case for 24 core Zen 6. Too many cores and if the f max of most cores is > 6GHz , then the paltry mid 4's to very low end 5 GHZ nT ranges that are being predicted in the chart above @200W-230W will still be well within the range where performance still scales fairly linearly with additional power. 200W will CERTAINLY be leaving a lot of performance on the table, thats why Im thinking will target 230W or even 250W+ (1 click PBO) with this thing. I maintain its going to be just like going Zen 3 to Zen 4 was, but to an even greater degree due to the 50% increase in core count.

 

[Josh128]

https://substackcdn.com/image/fetch/$s_!udpZ!,w_1456,c_limit,f_webp,q_auto:good,fl_progressive:steep/https%3A%2F%2Fsubstack-post-media.s3.amazonaws.com%2Fpublic%2Fimages%2Fb2a214eb-2da5-4c87-99b0-8279d5c9e4e5_1034x584.png

Examining Intel's Arrow Lake, at the System Level

Arrow Lake is the codename for Intel's newest generation of high performance desktop CPUs.

chipsandcheese.com

Nice. Looks like my "piece of sh*t" 9900X performs quite well on a technical level vs Intels latest and greatest 3nm "superior tile" technology CPU.

 

[511]

Nice. Looks like my "piece of sh*t" 9900X performs quite well on a technical level vs Intels latest and greatest 3nm "superior tile" technology CPU.

You do know that it is the botched L3 dragging the entire platform down alongside the bad fabric it's not the tile tech or 3nm at fault

 

[AMDK11]

AMD Ryzen 5 9600X & Ryzen 7 9700X Offer Excellent Linux Performance:​

AMD Ryzen 5 9600X & Ryzen 7 9700X Offer Excellent Linux Performance Review - Phoronix

www.phoronix.com

Quantifying The AVX-512 Performance Impact With AMD Zen 5 - Ryzen 9 9950X Benchmarks:​

Quantifying The AVX-512 Performance Impact With AMD Zen 5 - Ryzen 9 9950X Benchmarks Review - Phoronix

www.phoronix.com

Disabling Zen 5’s Op Cache and Exploring its Clustered Decoder:​

Disabling Zen 5’s Op Cache and Exploring its Clustered Decoder

Zen 5 has an interesting frontend setup with a pair of fetch and decode clusters.

chipsandcheese.com

Agner Fog:

Test results for AMD Zen 5​

Post 2025-07-26, 12:43:13


I have now finished testing the Zen 5. Thank you to the people who have helped running test scripts for me.

My test results for the AMD Zen 5 are impressive. It has a lot of features that increase different aspects of the CPU performance to new levels, never seen before.

Most importantly, the instruction fetch rate is increased from 16 to 32 bytes per clock cycle. The 16-bytes fetch rate has been a serious bottleneck in both Intel and AMD processors through many generations. The size of one instruction can be anywhere from 1 to 15 bytes. An AVX512 instruction can be from 6 to 11 bytes. This was a serious bottleneck since the rest of the pipeline could handle four instructions per clock cycle or more in earlier AMD processors as well as Intel processors. Only loops that fit into the micro-op cache could utilize the high throughput.

The Zen 5 can execute up to six instructions per clock cycle (rarely eight). Such a high throughput requires careful considerations from the software programmer to avoid long dependency chains. A dependency chain is a situation where each instruction depends on the result of the preceding instruction so that it is impossible to execute more than one instruction at a time.

The number of execution units is increased over previous models. There are six integer ALUs, four address generation units, three branch units, four vector ALUs, and two vector read/write units. All common instructions have more than one execution unit to choose between so that it will rarely have to wait for a vacant unit. It is possible to do six simple integer instructions per clock cycle. Vector instructions and floating point instructions can execute at a rate of two vector additions, two vector multiplications, and two vector read or write instructions simultaneously per clock cycle. All vector units have full 512 bits capabilities except for memory writes. A 512-bit vector write instruction is executed as two 256-bit writes.

Integer memory operations can execute at a rate of four reads per clock cycle or two reads and two writes. Floating point and vector memory operations can execute at the rate of two reads or writes per clock cycle, except for 512-bit writes.

The performance of branch instructions (if-then-else constructs) is also faster than anything we have seen before. The Zen 5 can execute two predicted taken branches or three predicted not-taken branch instructions per clock cycle. The branch predictor can look two branches ahead and it can decode both sides of a two-way branch simultaneously. Complicated repetitive branch patterns can be predicted after a short learning period.

The latency of integer vector addition has been increased from 1 clock cycle in Zen 4 to 2 clocks in Zen 5, while the latency of floating point addition is reduced from 3 to 2 clocks. Integer vector instructions and floating point vector instructions now have the same latencies.

While the CPU performance in terms of instruction fetch rate, decoding, execution units, memory read/write, and branch throughput is improved to new levels, there are only minor improvements in cache sizes and associativity. This means that CPU throughput is rarely a bottleneck in Zen 5, and the programmer has to focus on optimizing memory access if you want to utilize the high computing power of the Zen 5. The Zen 5 can give a significant performance boost to computation-intensive programs, while programs that are limited mainly by memory and disk access will not benefit much.

Detailed results are reported in my microarchitecture manual and instruction tables.

 

[Fjodor2001]

Me neither, but the "sweet spot"for 24 SMT2 cores that are supposedly able to reach 6GHz + handily is going to be HIGH. While the perf increase from Zen 4 and especially Zen 5 from 200W to 230W is not at all worth the extra 15% power consumption, that will NOT be the case for 24 core Zen 6. Too many cores and if the f max of most cores is > 6GHz , then the paltry mid 4's to very low end 5 GHZ nT ranges that are being predicted in the chart above @200W-230W will still be well within the range where performance still scales fairly linearly with additional power. 200W will CERTAINLY be leaving a lot of performance on the table, thats why Im thinking will target 230W or even 250W+ (1 click PBO) with this thing. I maintain its going to be just like going Zen 3 to Zen 4 was, but to an even greater degree due to the 50% increase in core count.

Well, I’m thinking that if ~105W was sweet spot for 16C, then with 24C it ought to be 50% more, so around 150-160W all else equal.

 

[511]

Well, I’m thinking that if ~105W was sweet spot for 16C, then with 24C it ought to be 50% more, so around 150-160W all else equal.

no? different node

 

[Fjodor2001]

no? different node

So what do you think the corresponding sweet spot will be for 24C Zen6?

 

[511]

It can be 120-135W but it's just a guess like pure guess

 

[Josh128]

Well, I’m thinking that if ~105W was sweet spot for 16C, then with 24C it ought to be 50% more, so around 150-160W all else equal.

If the cores had the same freq ceiling and v/f characteristics, I'd agree, but people here claim fmax will be above 6GHz. Some saying well above 6GHz. If thats true, sweet spot is going to be more than just +50% IMO. 200W sounds about right, but if thats the sweet spot, I highly doubt AMD is leaving an easy 10% nT perf on the table, if only for the optics. 230W or bust. I guarantee it.

 

[Josh128]

You do know that it is the botched L3 dragging the entire platform down alongside the bad fabric it's not the tile tech or 3nm at fault

All of it together is Arrow Lake, my friend. It is what Intel put out there.