Question Zen 6 Speculation Thread

[Geddagod]

No, its more than that. AMD cores now all have full avx-512, where P-cores do NOT. P-cores also do not have SMT and take more power compared to AMD.

Thats a lot of difference that needs to be noted in any comparison.

What an absurd reach. What does any of this, except maybe the first point, have to do with AMD's hybrid core strategy vs Intel's?
The level of discourse on this forum gets lower and lower by the day.

 

[Markfw]

What an absurd reach. What does any of this, except maybe the first point, have to do with AMD's hybrid core strategy vs Intel's?
The level of discourse on this forum gets lower and lower by the day.

I was replying to a post a few pages pack on P-cores and E-cpres that was comparing to AMDs core vs C-cores.

 

[poke01]

@Hulk i predict 73500

 

[jpiniero]

69420

 

[naukkis]

Can't be an "ultimate CPU" if L3 latency is severely degraded by being on another chip that has to communicate to the CPU over quite some distance, instead of being placed directly over or under the CPU chiplet.

At least to my understanding, that's how the Nova bLLC would be configured.

Intel ain't using any fancy tech in Novalake bLLC, it's just bigger die with extra cache.

 

[naukkis]

From what I've read bLLC will be limited to one tile, not the 52C version. Also AMD has largely mitigated any frequency loss with 3D cache, and if the rumored 9850X3D is true, it will not be an issue at all anymore.

Where you get those rumors? Nova Lake bLLC is just different die with extra cache and there's nothing preventing doing multi-chip with it. And using two large-cache chips to build 52c cpu with only two memory channels is only viable way to get some performance out.

 

[Josh128]

Intel ain't using any fancy tech in Novalake bLLC, it's just bigger die with extra cache.

Its still much further physically than X3D, which literally touches the cores vertically. bLLC is a given lateral distance, latency should be higher because of that.

 

[naukkis]

Its still much further physically than X3D, which literally touches the cores vertically. bLLC is a given lateral distance, latency should be higher because of that.

You are really buying AMD marketing. X3d is off-die stacked cache - AMD extra latency for it is something like 3 cycles. We don't know yet how Intel is implemented it's bLLC structurally - but it's a ondie cache which gives best possible latency and bandwidth until very large stacks where physical dimensions start to give edge to stacking. Stacking cache to existing die design is just much, much cheaper way to make big cache version - Intel this time didn't go cheap route but did absolutely best silicon they could to rival AMD.

 

[gdansk]

but it's a ondie cache which gives best possible latency

Does it, though? On die L3 for ARL-S is ~84 cycles and off die L3 for GR-X3D is ~52 cycles.
Larger capacity, faster access time and off die...

 

[511]

Let's have a little fun.
View attachment 132896

69000

 

[adroc_thurston]

Larger capacity, faster access time and off die...

calling SoIC stacks off-die is almost disingenious since it's like a 4c penalty for access there.

 

[511]

calling SoIC stacks off-die is almost disingenious since it's like a 4c penalty for access there.

It's physically on another die....

 

[Josh128]

You are really buying AMD marketing. X3d is off-die stacked cache - AMD extra latency for it is something like 3 cycles. We don't know yet how Intel is implemented it's bLLC structurally - but it's a ondie cache which gives best possible latency and bandwidth until very large stacks where physical dimensions start to give edge to stacking. Stacking cache to existing die design is just much, much cheaper way to make big cache version - Intel this time didn't go cheap route but did absolutely best silicon they could to rival AMD.

What marketing? Off die doesnt mean a damned thing when its directly connected below the cores with TSVs. Physics is not marketing, lol. You are talking about a sub 1mm distance from X3D cache to its connected core vs an unknown, but greater distance for a large laterally spaced on die (depends on the final tile size and configuration) cache. Distance=very big deal when speaking of cache latency.

 

[adroc_thurston]

It's physically on another die....

with direct interfaceless copper-to-copper bond.

 

[reaperrr3]

And AMD is doing 3d-stacking of L3 which brings its problems to the table.

Not really. The tech is getting fairly mature.
Sure, there are some minor limitations on clocks and voltage to avoid hotspots, but particularly the total latency is incredibly good for the amount of cache.
The physical distance to reach the farthest SRAM cells doesn't increase much, as only a small amount of verticality is added so data doesn't need to travel that much farther vs. regular L3.

A giant monolithic L3 like what Intel does with the 144MB variant on the other hand, means a single 2D layer of SRAM cells, so the physical distance of the farthest SRAM cells might be quite a bit larger than for AMD, which could hurt Intels already-poor L3 latency further.

Additionally, a large monolithic die has an inherently lower yield rate than a small CCD + small VCache stack, which are yielding and get binned separately.

Nevermind that by going on-die, Intel is obviously forced to produce all that cache on a much more expensive node with barely any SRAM density improvements, so Intels big-cache chip will be far more expensive to make.

Intel's L3 has not been good compared to AMD's for a long time now, so people probably don't have much faith in them.

Yeah. I mean, by now even their L2 compares terribly to AMD in terms of latency.

And games are rather cache-latency-sensitive.

Where you get those rumors? Nova Lake bLLC is just different die with extra cache and there's nothing preventing doing multi-chip with it.

Nothing preventing except.... cost, margin, and how much sense it makes in general.
And cost appears to be high enough that Intel weren't even sure about making the big-cache models at all, according to rumors.

And using two large-cache chips to build 52c cpu with only two memory channels is only viable way to get some performance out.

You're giving Intel too much credit.
The 52c is mostly a paper tiger to win some MT benchmarks and please some investors (and Intel shills), but it won't gain any traction outside some semi-professional niches, and maybe some die-hard pro-Intel rich kids.
Intel knows this, so they won't waste margin by using big cache dies on it.

The only relevant client workload where a huge L3 is worth the added cost is gaming, and please tell me how many games scale well beyond 24T and need more than 8 really fast cores for the heaviest threads.
Spoiler Alert: The 52c will be irrelevant for gaming.

 

[Hulk]

If you are already in the chart please provide the rest of your prediction data. Moving forward I'm only going to enter data if all data in red font is submitted so the chart is complete.

 

[naukkis]

What marketing? Off die doesnt mean a damned thing when its directly connected below the cores with TSVs. Physics is not marketing, lol. You are talking about a sub 1mm distance from X3D cache to its connected core vs an unknown, but greater distance for a large lateral on die (depends on the final tile size and configuration) cache. Distance=very big deal when speaking of cache latency.

There's a difference. On-die interconnect can operate at full speed silicon offers. Even best today silicon based off-die connections only can reliably do around 2GHz, wasting few clock cycles even in case of x3d where only cache arrays are off-die. On-die cache structures need to arranged to have interconnect being able to being physical reach time of target speed so whole L3-area with interconnect bus needs to be redesigned when changing cache structures radically so it's no wonder that Intel or AMD does not have done it before - it's extremely expensive silicon tweak for both designing and manufacturing point - but when done it should not have pretty much any handicaps for performance. I want to point out that what Intel is doing is really pushing limits to get performance at any costs - and that's nice thing to find if they still can sell that thing at somehow competitive prices.

 

[adroc_thurston]

by now even their L2 compares terribly to AMD in terms of latency.

No, Intel L2 is like 19 cycles and runs cclk.

 

[adroc_thurston]

On-die interconnect can operate at full speed silicon offers. Even best today silicon based off-die connections only can reliably do around 2GHz

?
V$ pads run at cache clock, which is core clock.

 

[naukkis]

A giant monolithic L3 like what Intel does with the 144MB variant on the other hand, means a single 2D layer of SRAM cells, so the physical distance of the farthest SRAM cells might be quite a bit larger than for AMD, which could hurt Intels already-poor L3 latency further.

They can do it just like AMD does, keep tags close and data array could be even off-die for minimal latency increase. L3 latency is something like 50 clock cycles, 3 additional clock cycles from going off-die won't matter and those 3 clock cycles would at least quadruple reachable silicon area in 2d-arrays.

 

[Thunder 57]

The amount of BS being spread in this thread is enough to lower IQ's. Just quit while you are behind.

 

[adroc_thurston]

They can do it just like AMD does, keep tags close and data array could be even off-die for minimal latency increase. L3 latency is something like 50 clock cycles

V$ slab has its own tags.

 

[Thunder 57]

Where you get those rumors? Nova Lake bLLC is just different die with extra cache and there's nothing preventing doing multi-chip with it. And using two large-cache chips to build 52c cpu with only two memory channels is only viable way to get some performance out.

So I used the word "limited" rather than saying Intel is rumored to only be making a bLLC version with one tile. IOW they are not making a 52 core bLLC version supposedly.

There's a difference. On-die interconnect can operate at full speed silicon offers. Even best today silicon based off-die connections only can reliably do around 2GHz...

Wrong. I don't know where you pulled that from but it couldn't be more wrong.

 

[gdansk]

It is very easy to believe AMD will continue their iterative improvements for vcache like they have been doing. For NVL who knows. Intel needs to design a 4 times bigger L3 and nearly cut access time in half.

But what's the bigger leap of faith?

 

[esquared]

They can do it just like AMD does, keep tags close and data array could be even off-die for minimal latency increase. L3 latency is something like 50 clock cycles, 3 additional clock cycles from going off-die won't matter and those 3 clock cycles would at least quadruple reachable silicon area in 2d-arrays.

This is an AMD Zen Spec thread. Not an Intel thread. Your last 9 posts yesterday and today
have been about Intel in an AMD thread.


esquared
Anandtech Forum Director