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Question Zen 6 Speculation Thread

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Cheesecake16 said:
AMD's opinion on AMX is very clear, just buy GPUs... They even had a TCO chart to that affect...
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But for geekbench they need an AMX unit.
Cheesecake16 said:
We know functionally very little about the Zen 6 core other than it will support VP2INTERSECT, that Zen 6 is likely Family 1Ah, and that the performance increase from the 9965 to the top of SKU Venice CPU is ~1.7x...
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We have an old slide for IPC target. Very meagre, not worth two year wait if it's as accurate for Zen 6 as it was for Zen 5.

Basically the hype train moved to 6555 fmax 😎 for a reason
 
gdansk said:
But for geekbench they need an AMX unit.
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they can just torture applelabs until they write proper AVX512FP16 ASM for ML subtests.
gdansk said:
Very meagre, not worth two year wait
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That's funny given that Pegasus is also high single digit to low teens without SME.
Too bad!
gdansk said:
Basically the hype train moved to 6555 fmax for a reason
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Gotta clock up, can't let ARMcels catch up in fmax.
 
Budget APUs are basic everything for basic platforms, AMD has Mendo here for eternity and I guess Bumblebee fits in the fancier part of this segment.

Mainstream APUs are CPU sticks with enough accel to satisfy whatever checklist MS feels like on the day, intended to be paired with green stickers for gamer(tm) laptops. This is where the Point family lives. MDS1-hi does get a very strong CPU for fancier green sticker machines or CPU focused T&L.

Desktop replacements use desktop CPUs with some tweaks. The Range family is here.

For Premium/Extreme T&L you got MDS P/H, both with class leading CPU and GPU configs, this is the most interesting part of the market with the most useful parts overall, so long as you have the cash. Corpos increasingly like these but also like the Intel tablet TDP parts, good for them.

Cheesecake16 said:
AMD's opinion on AMX is very clear, just buy GPUs... They even had a TCO chart to that affect...

We know functionally very little about the Zen 6 core other than it will support VP2INTERSECT, that Zen 6 is likely Family 1Ah, and that the performance increase from the 9965 to the top of SKU Venice CPU is ~1.7x...
Click to expand...
Well even if not official the leaks clearly point to 10% IPC as a baseline goal, Z4 did 13-14%, Z2 did 15%. To hit +70% socket perf you are going to need perhaps a little more than 10% unless the new memory/interconnect/uncore carry hard, or the clocks are utterly insane.
Z5 has glaring issues on the integer side that N2's xtor budget can fix.

gdansk said:
Which would be sad, if it took them two years to ship.
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Realistically it is 2 years, considering Oryon got delayed and launched with bad physdes.
Pegasus is slightly weaker than expected, M4 comfortably wins in Cinememe which I expected to be basically equal and I don't think it will quite hit 4.2k in GB which was also the expectation.
And it has to use SME to get there anyway, yuck.
SPEC is king for a reason.
I get it works for what ARM is targeting, but say would you rather 1-2 4k GB cores with the rest 3.5k or all cores to be 3.8k?
That is somewhat rhetorical but in server the latter is objectively better.
 
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branch_suggestion said:
Realistically it is 2 years, considering Oryon got delayed and launched with bad physdes.
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They're shipping their 2nd 3nm core a year after their 1st 3nm core. The plan is yearly new IP for phone chips.
Who knows how often they'll do laptop chips.

branch_suggestion said:
I get it works for what ARM is targeting, but say would you rather 1-2 4k GB cores with the rest 3.5k or all cores to be 3.8k?
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In laptop? Isn't everyone doing various mixes of cores?
 
adroc_thurston said:
The first 3nm core was just Phoenix with non-totally-busted physdes.
Pegasus is actually new doe.
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It's one year for phones. Which is, as I understand, where all the measurements come from so far.

poke01 said:
Honestly after seeing ARM cores this year, let AMD cook with Zen6. Theres no point in updating IP each year.
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Then they need to deliver the same cumulative gains. They won't.
I wonder why iterators keep winning. Even where AMD wins - servers - they're the most consistent iterator in that market.
 
gdansk said:
We have an old slide for IPC target. Very meagre, not worth two year wait if it's as accurate for Zen 6 as it was for Zen 5.
Click to expand...
So... functionally nothing is what you are saying...

branch_suggestion said:
Well even if not official the leaks clearly point to 10% IPC as a baseline goal, Z4 did 13-14%, Z2 did 15%. To hit +70% socket perf you are going to need perhaps a little more than 10% unless the new memory/interconnect/uncore carry hard, or the clocks are utterly insane.
Z5 has glaring issues on the integer side that N2's xtor budget can fix.
Click to expand...
The largest "issues" on the integer side is simply not enough registers which honestly you don't need N2 for... Realistically the largest bottleneck with Zen 5 is frontend latency which would need some... creative solutions assuming AMD doesn't increase the L1i cache capacity which they may or may not do...
 
Cheesecake16 said:
The largest "issues" on the integer side is simply not enough registers which honestly you don't need N2 for... Realistically the largest bottleneck with Zen 5 is frontend latency which would need some... creative solutions assuming AMD doesn't increase the L1i cache capacity which they may or may not do...
Click to expand...
Yeah the double pump scheme was always going to require some iterations to get good.
Doubling L1i would of course hide a lot of latency but is probably too drastic for a tick.
 
turtile said:
AMD already announced that Zen 7 will be released in 2027 with the MI500 series.
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No. They announced that a server CPU called Verano will be released in 2027 (along with the MI500 series, and a "next gen AI rack").

Some have speculated that Verano is Zen 7, others have speculated that Verano is another Zen 6 product.
 
Why can't it be Zen 6 with APX and AVX 10.2 an incremental update A16 is For Nvidia Fennyman AMD can use N2X
 
StefanR5R said:
No. They announced that a server CPU called Verano will be released in 2027 (along with the MI500 series, and a "next gen AI rack").

Some have speculated that Verano is Zen 7, others have speculated that Verano is another Zen 6 product.
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If I had to guess:
Normal Zen 6 CCDs with a new IOD (adding some ML/AI/HPC/Networking related features / accelerators) together with LPDDR6 support (LPCAMM2, increasing bandwidth by ~1.5x and improving power efficiency) and 100% PCIe 6.0 lanes (if not already the case with Venice).

These ML/AI platforms are not really CPU core performance limited (and Zen 6 will have plenty of that) but rather IO-Speed. Adding some new acceleration stuff could also make sense. Maybe we see stacked matrix accelerator chiplets on the IOD, which mimics Rubin CPX use cases. ~2.5 TB/s of 16-ch LPDDR6 is matching the bandwidth of a 512bit GDDR7 interface 😉 Native IF-Link support for CPU-only rack-scale clusters without any MI400/MI500 could be a thing as well (not sure for what use case).

Another option:
All of above including +50% CPU core count (12x 12C CCDs instead of only 8x).

So many options....
 
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