Question Zen 6 Speculation Thread

[Thibsie]

It's downard xDd with record losses

So why target AMD when the competitor is burning ? Trying to light sounder fires ?
C'mon...

 

[511]

So why target AMD when the competitor is burning ? Trying to light sounder fires ?
C'mon...

I never said Intel is successful just that AMD is not that successful as people make it out to be when you compare to Nvidia or TSMC and their respective market domination I would call AMD success if they take 50% of x86 market share with increase in revenue.

 

[gdansk]

AMD is not that successful as people make it out to be when you compare to Nvidia or TSMC

I don't know. People probably see things like this and assume they're very successful

 

[CouncilorIrissa]

I never said Intel is successful just that AMD is not that successful as people make it out to be when you compare to Nvidia or TSMC and their respective market domination I would call AMD success if they take 50% of x86 market share with increase in revenue.

Not hockey stick revenue curve = not successful, got it.
Stocks subreddit level take.

 

[511]

Not hockey stick revenue curve = not successful, got it.
Stocks subreddit level take.

That was the comparison is it not Nvidia TSMC AMD ?

 

[Markfw]

I don't know. People probably see things like this and assume they're very successful

The other problem is, that companies continue to buy Intel for servers,, as the saying "nobody ever got fired for buying Intel" has not died yet. And the installed base is so big that they just upgrade what they already have. This is changing, but not fast enough for AMD or people with half a brain.

 

[511]

The other problem is, that companies continue to buy Intel for servers,, as the saying "nobody ever got fired for buying Intel" has not died yet. And the installed base is so big that they just upgrade what they already have. This is changing, but not fast enough for AMD or people with half a brain.

Intel sell Enterprise Solution along with Software for their requirement I doubt AMD would put a serious dent there until they provide the same.

AMD should have gotten more market share with near 2X server performance but it's still slow and now they don't have massive lead.

 

[adroc_thurston]

Intel sell Enterprise Solution along with Software for their requirement

That's not really it, it's just a dinosaur market.

 

[Josh128]

What about Intel's growth ?

 

[OneEng2]

can you stop?
It TO'd eons ago.
They're all N2p besides mainstream mobile peanuts.

You keep saying this, but there has been nothing official to base this claim on.... so why would people stop speculating .... in a speculation thread?

Ive said this time and again, but Kepler, Adroc, and others insisted otherwise. I hope they are right. Maybe Pat and Lip Bu can save us all with 18A.

History would be on your side as well. AMD has not traditionally been using the beading edge node for consumer based high volume products.... only for Server where the margins are much higher.

Now, this doesn't mean that they wont do it, only that they haven't done it in the past.

Furthermore, if AMD believes it can best NVL with Zen 6 on N3P .... what purpose (other than leaving money on the table) would using N2P have?

In my experience, the vast majority of high core count usecases in DC come not from a single application scaling across all those cores, but more cores enabling more instances of a smaller application being run simultaneously.

This is exactly true.

My only debate is on the core counts for the full Zen 6 variants. It simply doesn't make any sense for AMD to go from Turin Zen 5 128c to Venice Zen 6 96c. Again, this doesn't terminate the possibility that they will do it. It only raises the question of why this speculation would be true.

There doesn't seem to be any technical road block from AMD creating a 16c version of Zen 6 full to make a 128c version of Venice full.

AMD should have gotten more market share with near 2X server performance but it's still slow and now they don't have massive lead.

Intel has been burrowing into the industry with sticky policies for decades. It's just taking a little time for these sticky policies to wear out IMO.

The dam has certainly broken IMO. At AMD's current rate, they will hold >90% of all new DC sales soon.

 

[adroc_thurston]

You keep saying this, but there has been nothing official to base this claim on.... so why would people stop speculating .... in a speculation thread?

That's a (You) problem.

Furthermore, if AMD believes it can best NVL with Zen 6 on N3P .... what purpose (other than leaving money on the table) would using N2P have?

Intel is whatever, it's like kicking toddlers around. There's fiercer comp elsewhere.

It simply doesn't make any sense for AMD to go from Turin Zen 5 128c to Venice Zen 6 96c

They don't.
It goes from Zen5 Turin 128c to Zen6 Venice 0c.
There's no classic SP7.

At AMD's current rate, they will hold >90% of all new DC sales soon.

Not even close.
50% unit share is like the stretch goal there.

 

[lucasworais]

50% unit share is like the stretch goal there.

Have they already surpassed 50% in revenue share?

 

[adroc_thurston]

Have they already surpassed 50% in revenue share?

Closing in on that.
But what they want is units cuz that's helluva lot harder for Intel to reclaim.

 

[reaperrr3]

History would be on your side as well. AMD has not traditionally been using the beading edge node for consumer based high volume products.... only for Server where the margins are much higher.

Now, this doesn't mean that they wont do it, only that they haven't done it in the past.

Not true.
Zen2 adopted N7 pretty much as soon as it became viable for more than phone chips.

Furthermore, if AMD believes it can best NVL with Zen 6 on N3P .... what purpose (other than leaving money on the table) would using N2P have?

Who says they believe that?

And come on, if N2P CCDs are smaller and can clock 7-10% higher, that absolutely allows for higher prices and margins, they'd probably leave more money on the table by using N3P.
That's a non-argument.

Nevermind that one issue you're ignoring is that with 12 cores and 48MB L3, N3P might simply not be dense enough to keep the CCD size compatible with the AM5 package, especially for the 2xCCD models, so the N2 logic transistor shrink might even be necessary in that regard, with the perf/efficiency as additional argument on top.

 

[branch_suggestion]

Not true.
Zen2 adopted N7 pretty much as soon as it became viable for more than phone chips.

Vega20 was even earlier, only just over 2 months after Apple for a much larger chip.

 

[adroc_thurston]

Vega20 was even earlier, only just over 2 months after Apple for a much larger chip.

how dare people forget the humble chadeon7

 

[Joe NYC]

History would be on your side as well. AMD has not traditionally been using the beading edge node for consumer based high volume products.... only for Server where the margins are much higher.

AMD just proved (to itself) that it can command high prices / high margins in 1 segment of client market.

New task, with Zen 6, is to extend it to other segments of client market.

 

[adroc_thurston]

New task, with Zen 6, is to extend it to other segments of client market.

no the design goal of Z6 client is populating the maximum amount of configs with minimal amount of tapeouts commited

 

[Joe NYC]

Nevermind that one issue you're ignoring is that with 12 cores and 48MB L3, N3P might simply not be dense enough to keep the CCD size compatible with the AM5 package, especially for the 2xCCD models, so the N2 logic transistor shrink might even be necessary in that regard, with the perf/efficiency as additional argument on top.

The chiplet will be right next to each other, almost no gap, no wasted space between chiplets.

 

[Joe NYC]

no the design goal of Z6 client is populating the maximum amount of configs with minimal amount of tapeouts commited

Yup, I am very impressed by this. The most efficient use of design resources.

Normally, this would also help with Time to Market, but in case of upcoming Zen 6 processors, the limiting factors may be:
- RDNA5 IP, for majority of APUs
- N2P / N2X volume ramp (for desktops)

 

[adroc_thurston]

RDNA5 IP, for majority of APUs

Minority.

N2P / N2X volume ramp (for desktops)

For everything pmuch.

 

[511]

Which product is N2X in 2026 lol there are no N2X products planned for 2026. Those are likely 2027.

 

[reaperrr3]

Yup, I am very impressed by this. The most efficient use of design resources.

Normally, this would also help with Time to Market, but in case of upcoming Zen 6 processors, the limiting factors may be:
- RDNA5 IP, for majority of APUs
- N2P / N2X volume ramp (for desktops)

The bulk of the mobile SKUs will only use the 8 RDNA3.5 CUs sitting in the N3P base SoC/IOD.
Desktop will likely use a simpler/cheaper IOD which will also use at best RDNA3.5.

And I suspect the Medusa Premium/Halo SKUs (aka those that use RDNA5) are 2nd half of 2027.

 

[511]

Desktop will likely use a simpler/cheaper IOD which will also use at best RDNA3.5.

With 155mm2 leaked die size for IOD and N4P it ain't cheap it's expensive than two Zen 5 CCD Combined alone.

 

[Joe NYC]

The bulk of the mobile SKUs will only use the 8 RDNA3.5 CUs sitting in the N3P base SoC/IOD.
Desktop will likely use a simpler/cheaper IOD which will also use at best RDNA3.5.

I can see that desktop IOD would be just fine with RDNA3.5. But I thought most of the mobile was using RDNA5.

If there are mobile SKUs with RDNA3.5, that definitely de-risks the launch of Zen 6. Launch can proceed just fine in mid 2026

Which really makes me wonder what's the point of Gorgon Point. If we are ~9 months away from launch of Zen6 mobile SKUs, what's the point of launching any more Zen 5 mobile SKUs in this short time window, when these Gorgon Point SKUs will overlap substantially with Zen 6.

It would make more sense if Gorgon Point was Zen 6 with RDNA3.5 and Medusa Zen 6 with RDNA5

And I suspect the Medusa Premium/Halo SKUs (aka those that use RDNA5) are 2nd half of 2027.

So. then, is AMD doing NPUs with majority of the mobile lineup, in all the pre-RDNA5 SKUs? That would extend the life of the NPUs, and mediocrity resulting from wasted die space for extra year at least.