Question Zen 6 Speculation Thread

[Joe NYC]

and need a bulletpoint for gen3 Vcache.
Ain't no way AMD's not gonna dangle the crackpipe in front of thirsty-thirsty gamers.

Gen 3?

Are Zen 3 and Zen 4 both considered Gen 1 and Zen 5 Gen 2?

Anything exciting with Gen 3? One thing that would make it a killer product is if TSMC and AMD mastered Wafer on Wafer packaging, which would cut cost and improve throughput on packaging dramatically. So that AMD could proliferate it more freely.

> 1 stack height - probably even more of a potential killer feature...

 

[adroc_thurston]

Gen 3?

yea

Are Zen 3 and Zen 4 both considered Gen 1 and Zen 5 Gen 2?

yeah.

Anything exciting with Gen 3?

You get more of it.

One thing that would make it a killer product is if TSMC and AMD mastered Wafer on Wafer packaging, which would cut cost and improve throughput on packaging dramatically. So that AMD could proliferate it more freely.

No, you're paying higher ASPs for V$ than ever.

> 1 stack height - probably even more of a potential killer feature...

Completely pointless.

 

[Thunder 57]

The pool goes from 32 MB for Zen 5c to 128 MB for Zen 6c

I remember there were performance gains in Zen 3 just from going to 2x16 MB to 1x32MB. So we may see a parallel here.



Comparing full Zen 6c vs. full Zen 5
- IPC: Zen 6c > Zen 5
- L3 per core: same
- local L3 pool: 4x the size for Zen 6c
- clock speeds: with node improvement, we could possibly expect Zen 6c ~= Zen 5

So performance per core of Zen 6c should be approximately equal to full Zen 5 in Turin.

And I remember the days when 32MB or 128MB was typical for total system memory. How times have changed.

 

[inquiss]

yea

yeah.

You get more of it.

No, you're paying higher ASPs for V$ than ever.

Completely pointless.

So it's easier to produce so you get more of it, but it's not wafer on wafer or double stacked?

Appreciate the cost to customer point. What they charge is irrelevant (ish) to how much it costs to make. There's no competition

 

[adroc_thurston]

So it's easier to produce so you get more of it

No lol you just get more cache stops.
We're going to a 12C CCX with 48M L3 baseline, after all.

but it's not wafer on wafer or double stacked?

It's WoW for Z5 too.

What they charge is irrelevant (ish) to how much it costs to make. There's no competition

Well it's just more of more expensive Si. It ain't free.

 

[LightningZ71]

I'm interested to see if they will produce an 8 core (recovery bin of 12) that keeps the full 48MB of L3, and if so, how it compares to the 9700x. I suspect that the combination of 50% more cache and better throughout will make a notable improvement in games.

 

[adroc_thurston]

I'm interested to see if they will produce an 8 core (recovery bin of 12) that keeps the full 48MB of L3

yeah they don't bin cache stops.

I suspect that the combination of 50% more cache and better throughout will make a notable improvement in games.

Better cores with lot more clocks too.

 

[LightningZ71]

Not since the 3100/3300x days that I know of. I don't recall seeing a consumer 4 active core CCD downbin for Zen3, though there might have been an OEM that I missed.

 

[Joe NYC]

You get more of it.

Ideally bigger percentage of CPUs with V-Cache will be sold

No, you're paying higher ASPs for V$ than ever.

The prices of Zen 5 V-Cache chips (9800x3d, 9950x3d) still hold at MSRP, while every other CPU is discounted. AMD is definitely doing something right.

Something to build on with Zen 6

Completely pointless.

Even if it does not deliver sufficient performance uplift, if it makes the competition do something foolish, it may be good just for that.

 

[Joe NYC]

It's WoW for Z5 too.

High Yield made a video on this, and his conclusion is (he was not 100% convinced but leaning to the opinion) that it is still not WoW.

Maybe there was some missing element or step that prevented that. If it is not WoW with Zen 5, but will be in Zen 6, it opens some mor volume possibilities, and also new design freedoms for all future chips.

Well it's just more of more expensive Si. It ain't free.

It's not just Si. There are metal layers, process steps, redundancy, yields. All make mostly SRAM wafer less expensive than a complex logic wafer.

If AMD can entrap Intel into fighting vertical SRAM capacity on N6 or N4 with horizontal N2 capacity, it's a win.

 

[OneEng2]

Well each core has 50% moar L3 to access if needed, they clock higher and IPC bump, so should be a fair battle. Memory is actually a wash with the clock uplift and MRDIMM.

Possibly since we are talking about Zen 6c vs Zen 5 full.

I still see no reason for AMD not to offer 128c of full Zen 6.... at least. If Diamond Rapids releases a 192 core version, it will likely stomp a 96c Zen 6 Venice IMO. I can't understand why everyone things AMD will let this happen all based on one unconfirmed leak.

And there, with same core count, Zen 6 could potentially run circles around Zen 5.

Yes, that may be true; however, I think it is only fair to consider the margin that is considered "run circles around".

Zen 6 full will likely face a 192c Diamond Rapids all P cores (without SMT). Lets say that a single Zen 6 amounts to 1.4 DMR cores. Zen 6 would have the equivalent of only 134 DMR cores and would be squashed by the 192c variant.

It just doesn't make sense.

So performance per core of Zen 6c should be approximately equal to full Zen 5 in Turin.

In what applications?

 

[adroc_thurston]

Ideally bigger percentage of CPUs with V-Cache will be sold

They're already like 90% of DIY sales.

The prices of Zen 5 V-Cache chips (9800x3d, 9950x3d) still hold at MSRP, while every other CPU is discounted. AMD is definitely doing something right.

Yeah.

Even if it does not deliver sufficient performance uplift, if it makes the competition do something foolish, it may be good just for that.

You think like a nerd. Don't.

High Yield made a video on this, and his conclusion is (he was not 100% convinced but leaning to the opinion) that it is still not WoW.

He's stupid because scribe lines match exactly. It is WoW bonding.

It's not just Si. There are metal layers, process steps, redundancy, yields. All make mostly SRAM wafer less expensive than a complex logic wafer.

All of that falls under 'Si'.

If AMD can entrap Intel into fighting vertical SRAM capacity on N6 or N4 with horizontal N2 capacity, it's a win.

Fighting what? Kicking Intel is like bludgeoning cripples with a hammer.

 

[marees]

I still see no reason for AMD not to offer 128c of full Zen 6.... at least.

How about this

Zen 6p ccd is a multiple of 12

128 is not a multiple of 12
(192 is)

 

[Joe NYC]

They're already like 90% of DIY sales.

Not in Asia. Japan, Korea, China. AMD needs to get young Chinese men on AMD processors.

He's stupid because scribe lines match exactly. It is WoW bonding.

Maybe we can get someone to ask AMD directly.

WoW could cut the packaging costs by ~90%. And with cost of 3D packaging becoming negligeable, more chips can be partitioned, so that there is a better fit between the process node and required performance. And, of course SRAM.

If cost of packaging is negligeable, then even mainstream CPUs, such as Kraken, that is estimated to be ~195 mm2 could become 2 dies of ~100 mm2 each, one of them cheaper, the other (on more advanced node) smaller. And both be higher yielding.

 

[adroc_thurston]

Not in Asia. Japan, Korea, China. AMD needs to get young Chinese men on AMD processors.

Yes in Asia.
Anywhere, really, 9800X3D rules the world with an iron fist.

WoW could cut the packaging costs by ~90%. And with cost of 3D packaging becoming negligeable, more chips can be partitioned, so that there is a better fit between the process node and required performance. And, of course SRAM.

No, WoW is faster but not really cheaper and you have other caveats in play.

If cost of packaging is negligeable, then even mainstream CPUs, such as Kraken, that is estimated to be ~195 mm2 could become 2 dies of ~100 mm2 each, one of them cheaper, the other (on more advanced node) smaller. And both be higher yielding

Straight to the wet nerd dreams he goes.
Pipe down.

 

[OneEng2]

How about this

Zen 6p ccd is a multiple of 12

128 is not a multiple of 12
(192 is)

LOL. Yes.

What I actually meant is that I see no reason that AMD would offer ONLY a 96c Zen 6p.

Everyone is on-board with the 96c variant which would be 8 CCD's each having 12c Zen 6p.

Why not have a 16c Zen 6p with 8CCD's giving you 128c Zen 6p? That makes a WHOLE LOT more sense than only using a 12c CCD and actually LOWERING core count from Zen 5.

Having a 12, 16, and 32 core CCDs actually makes a great deal of sense IMO.

This would make some really flexible product variants across markets.

 

[Doug S]

And I remember the days when 32MB or 128MB was typical for total system memory. How times have changed.

LUXURY! Back in my day 32KB or 128KB was typical for total system memory, and we had to turn a hand crank to power it because electricity hadn't been invented yet. And we liked it!

 

[adroc_thurston]

What I actually meant is that I see no reason that AMD would offer ONLY a 96c Zen 6p.

how the hell are you so dense.

Why not have a 16c Zen 6p with 8CCD's giving you 128c Zen 6p? That makes a WHOLE LOT more sense than only using a 12c CCD and actually LOWERING core count from Zen 5.

because 24c classic big CCD was killed. No one wanted it. Got it?

Having a 12, 16, and 32 core CCDs actually makes a great deal of sense IMO.

no it doesn't.

This would make some really flexible product variants across markets.

new TO for +4 cores is an idea so dumb you'd be fired on spot at AMD.

 

[igor_kavinski]

how the hell are you so dense.

You could say that the higher clocks coupled with more cache easily outperform 128 cores plus leaving some room to challenge and beat anything Intel may have up their sleeves, instead of making everyone suspect that you didn't get to spend enough time with your dad in your childhood.

because 24c classic big CCD was killed. No one wanted it. Got it?

Why didn't anyone want that?

new TO for +4 cores is an idea so dumb you'd be fired on spot at AMD.

So their tools aren't automated enough to make doing a TO easier than their competitors? Is AMD full of hateful people who snap at the slightest hint of a suggestion without explaining the demerits of it?

 

[adroc_thurston]

You could say that the higher clocks coupled with more cache easily outperform 128 cores plus leaving some room to challenge and beat anything Intel may have up their sleeves

For the 20th time over, they're different platforms.
They don't have to outperform or outdo or outsuck anything because they're different things made for different reasons.

instead of making everyone suspect that you didn't get to spend enough time with your dad in your childhood.

You sound pretty molested.

Why didn't anyone want that?

Fat sockets with tons of cores are what cloud wants. And they want Dense.

So their tools aren't automated enough to make doing a TO easier than their competitors?

No, they're just not gonna waste money and time to TO a CCD that serves the purpose of getting forum nerds hard.

Is AMD full of hateful people who snap at the slightest hint of a suggestion without explaining the demerits of it?

none of you are competent or important enough to 'explain' AMD the merit of anything.
you should stop because my capacity for laughter is limited.

 

[StefanR5R]

It has been said a few times now that

• with SP3 and SP5, AMD used one and the socket to cater to both the mainstream server market and to the "cram as much as you can into as few humongous sockets as possible, no matter what" markets (the latter are mostly hyperscalers),
• but with SP8, AMD will make an own socket for the mainstream server market.

*After* having considered that, AMD's choices of Zen 6 CCD types should make more sense to those who kept wondering.

 

[adroc_thurston]

It has been said a few times now that

• with SP3 and SP5, AMD used one and the socket to cater to both the mainstream server market and to the "cram as much as you can into as few humongous sockets as possible, no matter what" markets (the latter are mostly hyperscalers),
• with SP8, AMD will make an own socket for the mainstream server market.

*After* having considered that, AMD's choices of Zen 6 CCD types should make more sense to those who kept wondering.

more precisely they now have the volume and the enterprise traction to run a proper dual-track platform.

 

[Cheesecake16]

Fat sockets with tons of cores are what cloud wants. And they want Dense.

I wouldn't be surprised if there was a 96 core version on SP7 with 16 channels for Microsoft's HB and HX deployments and other HPC deployments if it isn't a MS exclusive like MI300C was...
But that is far from a standard deployment...

 

[adroc_thurston]

I wouldn't be surprised if there was a 96 core version on SP7 with 16 channels for Microsoft's HB and HX deployments and other HPC deployments if it isn't a MS exclusive like MI300C was...

I mean why not use normal SP7 Venice with 256c then?
You can like kill half the cores while still leaving a gig total of L3 online.

 

[Cheesecake16]

I mean why not use normal SP7 Venice with 256c then?
You can like kill half the cores while still leaving a gig total of L3 online.

I guess depending on what clocks SP7 Venice hits that is 100% possible... just that outside of HPC, 16 channels of MRDIMM with 1.6TB/s of memory bandwidth would be a struggle to use... and it does make sense for there to be a split of platforms... but there are high paying workloads like CFD, Sims, etc. which like high clocking SKUs because of licensing bullshit...