Question Zen 6 Speculation Thread

[Joe NYC]

Well, I think it's better to have less communication between CCDs.
It is better to keep that thread in one CCD
No matter how low the power consumption is, there is a reasonable cost.

This would be under a hypothetical scenario that a new algorithm is developed, where, for example, an unused portion of L3 of CCD1 could be used as a victim cache of CCD2, maybe as an L4.

In this hypothetical scenario, there would be a need for high bandwidth communication between the CCDs, and - conveniently - such a thing would be possible with Zen 6 InFO packaging.

 

[511]

Out of curiosity, do they have also highest usable bandwidth?

Yes as of right now this will disappear with Zen 6 though

 

[Thunder 57]

Yes as of rn this will disappear with Zen 6 though

Please use words. AFAIK rn doesn't translate into "right now". There are other people who may use an auto translater to help read and rn dossen't help.

 

[511]

Please use words. AFAIK rn doesn't translate into "right now". There are other people who may use an auto translater to help read and rn dossen't help.

You are giving me feeling that I am in a school 🤣

 

[Thunder 57]

Please use words. AFAIK rn doesn't translate into "right now". There are other people who may use an auto translater to help read and rn dossen't help.

And yes there is irony using AFAIK when saying words matter. That must be a PITA to non Engish speaking people. I think was said by a prominent person that abbreviations should be used less. (As Far as I know) ( Pain in the ass)

 

[DavidC1]

Please use words. AFAIK rn doesn't translate into "right now". There are other people who may use an auto translater to help read and rn dossen't help.

It's fine, you know why?

I bet 50%+ of the people on Anandtech arguing about PC Masterrace or wanting x86 over everything is typing all that on their phones!!

 

[LightningZ71]

I like how people just forget that Milan-X existed. A processor with multiple CCDs that all had VCache on them, just like what a few people are wanting on a hypothetical dual VCache CCD 9950X3D. Phoronix has many benchmarks where they demonstrate where this arrangement helps (and also hurts when it tanks clock speed).

It would help in those very same situations on desktop. There's just one problem: those situations are LARGELY (but not exclusively) use cases in server/DC workloads. Developers and small shops that focus on those areas would see a use.

There IS a use case for 4000 series EPYC parts to be made with two VCache CCDs. It probably isn't enough to pay for the validation work for it though.

It will NOT be any better for games than the normal 9950x3d.

 

[DrMrLordX]

I like how people just forget that Milan-X existed.

So did Genoa-X.

 

[branch_suggestion]

https://www.amd.com/en/blogs/2025/mrdimm--the-wrong-tool-for-today-s-memory-challenges.html

There's the truth... and, "the truth".

Turns out the author is ex-Micron lmao. Explains the rather vindictive tone for an AMD blogpost.

 

[Joe NYC]

Turns out the author is ex-Micron lmao. Explains the rather vindictive tone for an AMD blogpost.

It turns out that Micron is also the company that (together with Intel) developed the fake MRDIMM.

 

[Det0x]

Taken from the hydra discord


ES samples are out in the wild and interesting part about the two memory controllers in Zen6

 

[Josh128]

Taken from the hydra discord
View attachment 126923

ES samples are out in the wild and interesting part about the two memory controllers in Zen6

I believe MLID more than I do 1usmus, and I dont believe Zen 6 desktop samples have already been distributed. EPYC, I can believe, as we know AMD already has 2nm EPYC wafers in hand as of a month or so ago. Now, if Zen 6 desktop uses N3, I would agree its possible there are ES out there-- but that possibility also completely derails the "muh 6.5GHz 2nm gaming chip" hype train. Dont expect more than 6.0-6.2 GHz, you have been warned...

 

[Win2012R2]

se, suppose if developers got these new fangled dual V-cache CCD CPUs to tune their engines on, they could conceivably create a "pre-load" thread whose sole job would be to pre-cache stuff into the second V-cache

They tune for consoles - PS5 level with even more limited cache than bog standard 8 core Zen 5, that's how it's going to be for the next 10 years at least.

 

[igor_kavinski]

They tune for consoles - PS5 level with even more limited cache than bog standard 8 core Zen 5, that's how it's going to be for the next 10 years at least.

I don't see why they can't have an alternate tuned path for commodity x86 hardware.

 

[igor_kavinski]

It will NOT be any better for games than the normal 9950x3d.

Bold claim without testing at least 100 games using a variety of game engines.

 

[MS_AT]

Bold claim without testing at least 100 games using a variety of game engines.

That goes both ways. I haven't seen you buy Genoa-X and compare it to Genoa non X or 7950X3D locked to the same frequencies to show us the gains I mean that would bring the definitive end to this recurring discussion

I mean there is one thing I expect 9950X3DD (ee, I mean with dual CCD X3Ds) would do better than normal 9950x3D. Run 2 cache friendly games at the same time, as you could lock them both to separate CCDs and the game threads won't need to talk to each other across the CCD boundary.

 

[yuri69]

Taken from the hydra discord
View attachment 126923

ES samples are out in the wild and interesting part about the two memory controllers in Zen6

I like how he states Zen 6 is just an evolution of Zen 5. No hype trains in sight.

Regarding the those memory controllers, It's known upcoming server CPUs support both DDR5 and MR-DIMM.

 

[igor_kavinski]

That goes both ways. I haven't seen you buy Genoa-X and compare it to Genoa non X or 7950X3D locked to the same frequencies to show us the gains

It's not for lack of trying. I'm probably one of the few non-enterprise people always looking for a deal on 9184X. Still out of reach.

BUT I could do an easy test on my Epyc with 256MB cache. You just need to tell me how to run that test step by step like a 5 year old

 

[511]

It turns out that Micron is also the company that (together with Intel) developed the fake MRDIMM.

View attachment 126922

after looking a bit online it's the same stuff and more than likely Intel was a big Part in development with Micron and SK Hynix and they just ratified one standard for their own and one for JEDEC kind of USB 4.0 and TB lol

 

[igor_kavinski]

I mean there is one thing I expect 9950X3DD (ee, I mean with dual CCD X3Ds) would do better than normal 9950x3D. Run 2 cache friendly games at the same time, as you could lock them both to separate CCDs and the game threads won't need to talk to each other across the CCD boundary.

I like that name! I'm making it official until AMD fires a shot.

So the 9950X3DD could also show its mettle with a game where the main thread is pinned to one CCD and all other game threads are pinned to the second CCD, leaving more cache available to the main game thread. But thread pinning (rather than process pinning) is not user configurable I think (correct me if wrong) so this is something the developer will need to do explicitly in their code.

 

[igor_kavinski]

Regarding the those memory controllers, It's known upcoming server CPUs support both DDR5 and MR-DIMM.

If there are two memory controllers in the consumer Zen 6 IOD, then that's most likely for DDR5 and DDR6.

Could SERIOUSLY point to DDR6 launching for consumer in H2 2026!

 

[igor_kavinski]

I believe MLID more than I do 1usmus, and I dont believe Zen 6 desktop samples have already been distributed.

At least one guy on this forum may have them and he's not spilling any beans

 

[511]

At least one guy on this forum may have them and he's not spilling any beans

wonder who that is

 

[igor_kavinski]

wonder who that is

Don't look at me. If I had it, my posts here would be like:

I think Zen 6 may hit these speeds. I won't say why but TRUST ME BRO

 

[Win2012R2]

I don't see why they can't have an alternate tuned path for commodity x86 hardware.

Because they don't have time and their primary objective is to get it working on PS5 now.

Could SERIOUSLY point to DDR6 launching for consumer in H2 2026!

No chance.