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Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

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igor_kavinski said:
Yeah but we need 512MB of that. At least I won't be satisfied till that happens
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In general, the miss rate on a last level cache halves as the size of the cache quadruples. For example, if your hit rate on a 512Kb cache was 90%, your miss rate would be 10%. If you doubled that cache twice, to 2 MB, you would improve the miss rate to 5% and the hit rate to 95%. It would make a noticeable difference only in programs that have a hot working set that now fits in the expanded cache, but spilled before. Those are very general numbers for x86 code as the effect is still HIGHLY dependent on the hot working set size of each program.

Be aware that, for every doubling of cache size, you are going to introduce additional access latency as well as additional latency in any memory operations that result from a miss when seen from the program itself, OR, you will make the design of the cache more complex, taking up more area, resulting in additional product cost. Eventually, you just aren't making any useful impact in working set latencies and will have to resort to LOTS of predictive extra data loads from main memory to attempt to preload the cache with data that you think that the program will need next. This burns up a lot of energy making memory calls that are often unneeded.

I think that AMD is currently happy with their L3 cache ratio and may look to maintain that ratio into larger CCXs with respect to VCache packages.
 
LightningZ71 said:
Eventually, you just aren't making any useful impact in working set latencies and will have to resort to LOTS of predictive extra data loads from main memory to attempt to preload the cache with data that you think that the program will need next. This burns up a lot of energy making memory calls that are often unneeded.
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This should be exposed as a BIOS option and let the users make that call. I personally have no issue burning a few extra watts for maximum performance.
 
I vaguely remember from long ago that there were processors that had bios settings where you could turn cache prefetch on and off. It's been a minute, I've slept since then, and there may have been an alcohol or two in my system along the way, so that's about all I have at the moment.
 
LightningZ71 said:
I vaguely remember from long ago that there were processors that had bios settings where you could turn cache prefetch on and off. It's been a minute, I've slept since then, and there may have been an alcohol or two in my system along the way, so that's about all I have at the moment.
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It should be available on AM5. Usually the option can be found from AMD specifc menu but your mileage may vary, depending on the manufacturer.
 
MS_AT said:
from techtechpotato stream or somebody shared a link to japanese site around the same time, that reprinted most of the slides if I remember correctly. In the stream you have both the article (skip backward) and the presentation slides.
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Bottom line, which is better, 18a or N2 ?
 
www.servethehome.com

AMD Ryzen 9 9950X3D Review

In our AMD Ryzen 9 9950X3D mini review, we see what the new 16-core 32-thread 3D V-Cache parts offer compared to previous generations
www.servethehome.com www.servethehome.com

With all of this said, if AMD gave us the option to have 3D V-Cache on both CCDs so that we could avoid having one set of lower cache and one set of higher cache cores, I think a lot of folks would be interested.
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Hail The Brain Slug said:
But... anyone who thinks they want that is ignorant and a fool.
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I never said that. I know a lot of people want to see it. I just don't think it'll end up resulting in what they expect.

Look at the 9950X3D. It's no better in productivity than a 9950X in just about everything. Why would a dual Vcache version be any different? It would just be a waste of Vcache when AMD can't keep them in stock.
 
Thunder 57 said:
I never said that. I know a lot of people want to see it. I just don't think it'll end up resulting in what they expect.

Look at the 9950X3D. It's no better in productivity than a 9950X in just about everything. Why would a dual Vcache version be any different? It would just be a waste of Vcache when AMD can't keep them in stock.
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That you feel singled out here is extremely telling.
 
MS_AT said:
What would be better
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The answer is trivial: The operating system and the userland gets to deal with sixteen homogeneous cores.¹
Or, what @Win2012R2 said while I was distracted.

Thunder 57 said:
Even on regular dual CCD CPU's one chiplet is binned better and runs at a higher frequency.
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Not in EPYCs AFAICT.

________
¹) although split into two last-level cache domains, a problem for which at least EPYC 7000 and 9000 BIOSes offer an optional NUMA setting; don't know about EPYC 4000 BIOSes
 
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