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Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

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The X3D parts will be the new gaming champs.

AMD has the ability to churn out XT type chips if Intel should actually end up being significantly faster. I doubt they will, as Arrow Lake does not move the performance needle much due to the need for Intel to focus on perf/watt for a change.

Status Quo maintained. Sucks for consumers. Good for investors.
 
eek2121 said:
You guys didn’t even notice the clocks in the screenshot, did you?
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Oh, that's certainly a nice boost. I'm more interested in what clocks the X parts can maintain. Coupled with the I/O improvements with the recently noted kernel patch, those should be notably impressive.
 
techjunkie123 said:
Can you explain? I see 4.1 GHz at 1.01 V. How does that compare to Zen 4/Zen 5 desktop chiplet?
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Well top-end 128C Genoa (the 9754) tops out at 3.1. This one has 4.1. Not sure if that's an all-core boost, but it's a significant gain from the clocks alone.

Which is interesting. Does B1 somehow have a massively better v/f curve compared to B0?
 
CouncilorIrissa said:
Well top-end 128C Genoa (the 9754) tops out at 3.1. This one has 4.1. Not sure if that's an all-core boost, but it's a significant gain from the clocks alone.

Which is interesting. Does B1 somehow have a massively better v/f curve compared to B0?
Click to expand...

Really interesting, why continue to produce the B0 parts for desktop? Since it's the same CCD, maybe it was a time to market thing and Turin gets the latter stepping first and since there is no point still producing B0 later on, desktop gets B1 once initial run of B0 is sold out?
 
CouncilorIrissa said:
top-end 128C Genoa (the 9754) tops out at 3.1
Click to expand...
That's Bergamo, not Genoa.

CouncilorIrissa said:
This one has 4.1. Not sure if that's an all-core boost, but it's a significant gain from the clocks alone.
Click to expand...
64c Genoa, if switched to cTDP_high = 400 W, reaches its f_max of 3.7 GHz in some lighter workloads on all threads. Extrapolating from that, 128c Turin might run at 4.1 GHz with similarly light workloads on 50% of the SMT threads, as a guess.

CakeMonster said:
Do we know if the X3D cache will help with the added inter-core and inter-CCD latency in Z5?
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"We", as in "the unwashed masses", don't know that. The regression of the concurrent CMPXCHG microbenchmark may or may not be connected with the area reduction of on-CCD L3$. ("We" are still in the dark how AMD achieved this reduction.) Stacked cache removes area constraints, so there is that. But I doubt that stacked cache would be used to reintroduce performance related functionality which was perhaps (or perhaps not) cut from the on-CCD cache.
 
Markfw said:
I have a 64 core Turin on the way, it will be here Friday, so I will update my Turin build thread at that time. (weel, after a couple of days to put it in)
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Can we give you a long list of benchmarks to run on it or are you going to put it immediately to DC work as you typically do? 😛

If it's the running part that's hard for you (because all that waiting for benchmarks to finish can test anyone's patience), would you be willing to let some trusted member here login to your machine remotely and run benchmarks for a couple of days before you get your DC workloads running?
 
igor_kavinski said:
Can we give you a long list of benchmarks to run on it or are you going to put it immediately to DC work as you typically do? 😛

If it's the running part that's hard for you (because all that waiting for benchmarks to finish can test anyone's patience), would you be willing to let some trusted member here login to your machine remotely and run benchmarks for a couple of days before you get your DC workloads running?
Click to expand...
One of the first benchmarks will be 8 8C tasks (thats 64 threads used, and lasso disables SMT for this, so all the CCD cache can be used by one process), then cb 24, then only those that I have free access to.
 
StefanR5R said:
That's Bergamo, not Genoa.


64c Genoa, if switched to cTDP_high = 400 W, reaches its f_max of 3.7 GHz in some lighter workloads on all threads. Extrapolating from that, 128c Turin might run at 4.1 GHz with similarly light workloads on 50% of the SMT threads, as a guess.
Click to expand...
Thanks for the correction, I completely forgot that Genoa topped out at 96C.
 
Its one of these 2, specifically this part number
AMD EPYC 9555Zen 564 / 128256 MB3.30 GHzDDR5-6000360W
AMD EPYC 9535Zen 564 / 128256 MB3.50 GHzDDR5-6000300W
100-000001247-12 part
 
StefanR5R said:
64c Genoa, if switched to cTDP_high = 400 W, reaches its f_max of 3.7 GHz in some lighter workloads on all threads. Extrapolating from that, 128c Turin might run at 4.1 GHz with similarly light workloads on 50% of the SMT threads, as a guess.
Click to expand...
On the screenshot you can see that it is 2 socket configuration with each socket having 128 cores with SMT disabled. So this frequency doesn't have to be anything special
1724188072848.png
 
Markfw said:
For one, we have no idea the %load of these 2, so its virtually meaningless. I have a 64 core Turin on the way, it will be here Friday, so I will update my Turin build thread at that time. (weel, after a couple of days to put it in)
Click to expand...
How is that even possible considering it has even been announced yet? lol Serious question, what are the requirements for getting a sample like that?
 
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