Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[Markfw]

How is that even possible considering it has even been announced yet? lol Serious question, what are the requirements for getting a sample like that?

ebay ES

Pardon Our Interruption...

 

[Hitman928]

https://twitter.com/x/status/1825859218802618610

 

[Saylick]

So Turin will use 12 channels of "sweet spot" DDR5-6000???

SWEEEEEEEEEEEETTTTTTTTTTTTT!!!!!!!

Relax... relax.

Seems like seeing those Turin specs also hit your "sweet"-spot.

 

[Timmah!]

So no info on the inter-CCD latency issue yet? Whether thats actually a bug, or a feature?

 

[eek2121]

@Timmah! probably as designed, but it really doesn't matter as much as folks claim. Zen 5 is faster than Zen 4 (how much depends on your workloads, gamers not happy...yet, AI guys super happy! Everyone else is between those two folks) The chip generally is an upgrade in many scenarios, albeit a minor one.

Honestly, EPYC and Threadripper are going to be exciting for non-gamers/non casual users. For everyone that doesn't need an upgrade now? Just wait.

Also, (sorry, offtopic) side note: I guess SarahKerrigan is gone?

 

[Josh128]

So the higher power consumption of Zen 5 carries to EPYC. 9654 Genoa was 2.4Ghz base, 360W TDP. 9655 Turin is 2.6GHz base, but 400W(!) TDP. Thats 11% more power, I'd be very curious to see the average uplift-- probably wont be much more than 11%, so the perf/power will likely be very similar to last gen.

Whats going to be really interesting is what 128 core 3nm Zen 5C (if they make such an SKU) can do vs 128 core 4nm Zen 4C. I expect it to be the most interesting comparison of this whole generation.

 

[marees]

"While I only dug into additional performance monitoring events on a few cores, I hope AMD will increase the L1 instruction cache’s size later on. Going to 64 KB probably isn’t enough. Apple and Qualcomm have gone for very large 192 KB L1 instruction caches, and with good reason. But even that won’t be enough to contain the instruction footprint on certain workloads."

Zen 5 Variants and More, Clock for Clock

Zen 5 is AMD’s newest core architecture.

chipsandcheese.com

 

[eek2121]

So the higher power consumption of Zen 5 carries to EPYC. 9654 Genoa was 2.4Ghz base, 360W TDP. 9655 Turin is 2.6GHz base, but 400W(!) TDP. Thats 11% more power, I'd be very curious to see the average uplift-- probably wont be much more than 11%, so the perf/power will likely be very similar to last gen.

Whats going to be really interesting is what 128 core 3nm Zen 5C (if they make such an SKU) can do vs 128 core 4nm Zen 4C. I expect it to be the most interesting comparison of this whole generation.

See earlier posts. Much greater than 11%.

 

[itsmydamnation]

So the higher power consumption of Zen 5 carries to EPYC. 9654 Genoa was 2.4Ghz base, 360W TDP. 9655 Turin is 2.6GHz base, but 400W(!) TDP. Thats 11% more power, I'd be very curious to see the average uplift-- probably wont be much more than 11%, so the perf/power will likely be very similar to last gen.

Whats going to be really interesting is what 128 core 3nm Zen 5C (if they make such an SKU) can do vs 128 core 4nm Zen 4C. I expect it to be the most interesting comparison of this whole generation.

TDP and base clock have to account for AVX 512 implementation , which is substantially bigger then Zen4.

 

[Markfw]

See earlier posts. Much greater than 11%.

3.3 ghz way more than 9654

 

[Thunder 57]

"While I only dug into additional performance monitoring events on a few cores, I hope AMD will increase the L1 instruction cache’s size later on. Going to 64 KB probably isn’t enough. Apple and Qualcomm have gone for very large 192 KB L1 instruction caches, and with good reason. But even that won’t be enough to contain the instruction footprint on certain workloads."

Zen 5 Variants and More, Clock for Clock

Zen 5 is AMD’s newest core architecture.

chipsandcheese.com

I found that curious. Those chips lack uop caches, right? Hence the need for a larger L1i. Zen originally had a 64KB L1i but shrunk it to 32KB in Zen 2 to make room to increase the uop cache size.

 

[Hotrod2go]

These caches are indeed faster, and L1d has become bigger. (And it doesn't stop at these caches, as e.g. BTB is bigger, ITLB is bigger, µop cache is dual ported, ROB is larger...) *However*, bigger L1 and faster L1/2/3 are benefiting workloads more which hit L1/2/3 a lot, whereas the returns are diminishing in workloads which have a sizable amount of cache misses to begin with. This goes without saying but I am mentioning it because you brought up games. Many video games empirically benefit from increase of L3 cache size and from decrease of main memory latency. So they are more akin to the latter type of workload.

Yes, I get your point, but I don't play "many games" I'm a Bethesda game fan & with their latest release - Starfield & its creation 2 engine I notice an increase in fps with my 9700X using the same memory profile as before with Zen 4. So its engine specific if its noticeable the increased cache efficiency at all levels of it.

 

[Hotrod2go]

You can load from L1 128B/c with AVX512, 64B/c with AVX2 and 32B/c with pure scalar code. For Zen4 it was respectively, 64B/c, 64B/c, 24B/c.
Now about AIDA it's testing aggregate bandwidth so comparing 6 cores to 8 cores will leave you with false assumptions as 8 core will most likely show greater score due to having more cores.
Games won't see such dramatic increase in BW as AIDA might let you believe as they are rarely using SIMD and none of them are using AVX512. For games latency improvements are more welcome.

The latest iteration of non beta Aida64 warns the end user it is not optimised for Zen 5 yet. So take my claims as a guide only at this point in time. I'm well aware synthetic benchmarks have some detachment from real world scenarios.

 

[StefanR5R]

@StefanR5R , what NUMA settings do you recommend in the server BIOS for getting best performance out of consumer workloads/benchmarks, as opposed to NUMA-aware server workloads?

Impossible to say for me, because I have no own experience with Windows on NUMA machines, or even on machines with split last-level caches.

So Turin will use 12 channels of "sweet spot" DDR5-6000???

SWEEEEEEEEEEEETTTTTTTTTTTTT!!!!!!!

Nice, I thought the rumors said 5600 or something like that.
But timings of reg-ECC kits will probably be a shock to gamers to see. ;-) They should wait for Turin-X anyway. :-D

On the screenshot you can see that it is 2 socket configuration with each socket having 128 cores with SMT disabled. So this frequency doesn't have to be anything special
View attachment 105843

The thing with xwitter references is, one might be unable to follow such links, or the web browser at hand might not show anything.

So the higher power consumption of Zen 5 carries to EPYC.

Higher power consumption compared to what? (Rhetoric question. Always look at work gotten done for the power.)

9654 Genoa was 2.4Ghz base, 360W TDP. 9655 Turin is 2.6GHz base, but 400W(!) TDP.

Gasp! (Not really.)
If you put a vectorized workload onto Genoa, then even the 64 core SKU still runs very efficiently when set to its cTDP_high of 400 W. Guess what AMD's guides have always been recommending WRT the choice between cTDP_low/default TDP/cTDP_high of all the EPYC generations when you use them in HPC and similar scenarios.

Personally I am interested to see which cTDP_high the 64 core Turin will have. IMO, 500 W could be reasonable given the considerably wider core and to be expected core throughput compared to Genoa. — Edit: Running the IMCs at higher clock rate will certainly demand a decent amount of more power too. Sometimes it pays off to configure a lower RAM clock rate than the maximum supported.

 

[MS_AT]

The thing with xwitter references is, one might be unable to follow such links, or the web browser at hand might not show anything.

Sure, just wanted to point it out until we get another hype train

 

[Josh128]

Higher power consumption compared to what? (Rhetoric question. Always look at work gotten done for the power.)

Zen 4. Its already established that low clock / TDP Zen 5 is scarcely better than Zen 4 at all in perf/w (7700 vs 9700X @65W), and actually can be worse at low enough TDP. Being that these server chips core frequencies are way down compared to desktop, way lower than what desktop can do at 65W, they are very possibly dropping near that "worse than" range.

 

[Josh128]

See earlier posts. Much greater than 11%.

Performance? Outside of AVX-512 acceleration, core for core, no way.

 

[CouncilorIrissa]

Performance? Outside of AVX-512 acceleration, core for core, no way.

In server workloads it's much higher than 11%.

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[StefanR5R]

Zen 4. Its already established that low clock / TDP Zen 5 is scarcely better than Zen 4 at all in perf/w (7700 vs 9700X @65W), and actually can be worse at low enough TDP.

Oh, you were referring to the sketchy scaling of GNR (and STX I think) to low per-core power levels. Yes, it will be interesting to see how Turin will manage. At the top end, there is a core count increase, the IOD will support faster RAM, the top end has more fabric links active... and at the same time the cores are that much wider. Quite some places to spend additional socket power at. Potentially one out of several debatable points why Turin gets a newer CCD stepping.

 

[Timmah!]

In server workloads it's much higher than 11%.

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Page 735 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

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Most of us here, though, dont run server workloads

 

[GTracing]

Most of us here, though, dont run server workloads

If you follow the discussion, the first comment was specifically about server workloads.

 

[Josh128]

If you follow the discussion, the first comment was specifically about server workloads.

Actually, my comment was about general performance increases from Genoa to Turin, not performance in server workloads. Yes, indeed these are server chips, but there are plenty of scientific applications that might be run on these chips that are not server specific.

 

[igor_kavinski]

ASUS 'accidentally' lists Ryzen 9000X3D series on AMD 800-Series motherboard microsite - VideoCardz.com

ASUS ready for the next-gen Ryzen 9000X3D series At least the motherboard microsite page is. As discovered by @momomo_us, ASUS has ‘accidentally’ listed the Ryzen 9000 X3D series on its microsite, which launched yesterday for the new 800-series motherboards. The website not only mentions the...

videocardz.com

Wonder if AEMP is EXPO 2.0 or just some ASUS marketing term.

@Det0x, tell us more

 

[eek2121]

Performance? Outside of AVX-512 acceleration, core for core, no way.

Boost clocks for EPYC alone increase by more than 11%. 3.7 -> 4.5 ghz is a huge jump. I am expecting Threadripper to have a peak of at least 5.5ghz and will be sad if that is not the case.

Just because client is boring right now doesn’t mean all segments are.

side note: Postgres added AVX-512 support to some areas and managed more than a 6x performance increase in some cases. SQL databases can benefit significantly by utilizing AVX-512.

 

[blackangus]

Boost clocks for EPYC alone increase by more than 11%. 3.7 -> 4.5 ghz is a huge jump. I am expecting Threadripper to have a peak of at least 5.5ghz and will be sad if that is not the case.

Just because client is boring right now doesn’t mean all segments are.

side note: Postgres added AVX-512 support to some areas and managed more than a 6x performance increase in some cases. SQL databases can benefit significantly by utilizing AVX-512.

This is interesting and super good to know, Thanks!