Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[Kolifloro]

Are you just writing nonsense or do you state with certainty, that AMD will present us a 24% IPC increase?

I am afraid ... I was just SPECULATING ...


Regards. 🙂

 

[eek2121]

Threadripper Zen 5 When??? lol it is going to be a long wait.

 

[techjunkie123]

Do we have any leaks on how strix will compare to Phoenix in terms of battery life under light - medium loads?

I'm really curious what the power/performance curves for Zen 5 will be like. Hopefully they're better than Phoenix and the uncore power is also better!

 

[Fjodor2001]

If Zen5 X3D will be released already in September, are any of you intending to buy the vanilla variant in July anyway and if so why?

 

[DisEnchantment]

The bean counters are counting the mm2 at AMD.
Then there are lamentations and the weeping and gnashing of teeth for the non believers of the bigly IPC gainz

 

[Henry swagger]

View attachment 101536

The bean counters are counting the mm2 at AMD.
Then there are lamentations and the weeping and gnashing of teeth for the non believers of the bigly IPC gainz

Why cut down the structures ? .. zen 4 was well designed for its size 🤔

 

[Mopetar]

If Zen5 X3D will be released already in September, are any of you intending to buy the vanilla variant in July anyway and if so why?

I think that's going to depend more on how those parts stack up against the 7800X3D for many people.

AMD has already stated that they don't expect their new CPUs to handily beat the Zen 4 v-cache parts, so I think unless there are some important titles where the new parts are clear winners, that few people will be tempted to upgrade.

Anyone on an older platform will just go for the best chip, even if it's an older Zen 4 CPU since it's the same platform either way. Maybe some people will consider Zen 5 if it's cheaper for similar performance, but the only people who I think will definitely upgrade are those running a lot of AVX-512 code as that's the most obvious advantage that Zen 5 brings to the table.

 

[gdansk]

Counting the mm2 but double vector bandwidth and a full rate AVX-512?
Doesn't really add up, dis. Seems like a pretty easy cut if they wanted to save area at all costs.
They added some places and took away in other. But that's not unusual.

 

[H433x0n]

View attachment 101536

The bean counters are counting the mm2 at AMD.
Then there are lamentations and the weeping and gnashing of teeth for the non believers of the bigly IPC gainz

Who is this guy? Is he credible and in a position to know?

I’m guessing the numbers provided to OEMs were the 10-15% range we’ve seen before.

 

[CouncilorIrissa]

Counting the mm2 but double vector bandwidth and a full rate AVX-512?
Doesn't really add up, dis. Seems like a pretty easy cut if they wanted to save area at all costs.
They added some places and took away in other. But that's not unusual.

Probably a consequence of running the same design on client and server (full rate AVX-512). Good for Turin, but not that relevant for GNR and STX.

 

[jpiniero]

Counting the mm2 but double vector bandwidth and a full rate AVX-512?
Doesn't really add up, dis. Seems like a pretty easy cut if they wanted to save area at all costs.

AI AI AI

 

[Goop_reformed]

Who is this guy? Is he credible and in a position to know?

I’m guessing the numbers provided to OEMs were the 10-15% range we’ve seen before.

https://twitter.com/x/status/1803815525455192245

 

[DisEnchantment]

Probably a consequence of running the same design on client and server (full rate AVX-512). Good for Turin, but not that relevant for GNR and STX.

For the Mobile versions, looks like a possibility that they cut L3 cache and some PRF as well, possibly to cut power and cost.

 

[H433x0n]

https://twitter.com/x/status/1803815525455192245

Yeah, I know of him he's credible. He's done a lot of good work in the past.

 

[CouncilorIrissa]

For the Mobile versions, looks like a possibility that they cut L3 cache and some PRF as well, possibly to cut power and cost.

Cutting the PRF (or any other core-private resource for that matter) would be a first for any Zen IIRC?

 

[SarahKerrigan]

Cutting the PRF (or any other core-private resource for that matter) would be a first for any Zen IIRC?

And would be extremely out of character for how AMD has generally worked.

I expect Zen 5 to largely just be Zen 5, not "here's Zen 5 but with fewer physical registers here, a smaller scheduler there, an extra cyc of latency on the FMA..."

 

[gdansk]

AI AI AI

Zen 5 was planned before the latest AI meme. And if they were all about wasting area for AI they'd have added something like AMX.

 

[CouncilorIrissa]

And would be extremely out of character for how AMD has generally worked.

I expect Zen 5 to largely just be Zen 5, not "here's Zen 5 but with fewer physical registers here, a smaller scheduler there, an extra cyc of latency on the FMA..."

Yes, usually they design a core and that's what you get across the entire product stack. I think they only customised the FPU for PS5, but that's semi-custom business.

 

[SarahKerrigan]

Yes, usually they design a core and that's what you get across the entire product stack. I think they only customised the FPU for PS5, but that's semi-custom business.

Yep. Thing is, parameterization of stuff like that often costs more in dev/validation than you save in an incrementally smaller core variant. AMD has been wise to mostly avoid it thus far.

I think anyone believing that Strix Zen 5 will somehow be a materially worse microarchitecture than desktop Zen 5 is going to be disappointed.

 

[jpiniero]

Zen 5 was planned before the latest AI meme.

True. But there was enough time to gimp the L3, right?

It makes sense. TSMC isn't getting any cheaper so penny pinching on mm2 is only going to get worse. Strix Point laptops are already expensive enough as it is.

 

[Kepler_L2]

True. But there was enough time to gimp the L3, right?

It makes sense. TSMC isn't getting any cheaper so penny pinching on mm2 is only going to get worse. Strix Point laptops are already expensive enough as it is.

We already know Strix L3 (16MB for Zen5 CCX, 8MB for Zen5c CCX).

 

[gdansk]

True. But there was enough time to gimp the L3, right?

Gimp how?

 

[CouncilorIrissa]

True. But there was enough time to gimp the L3, right?

It makes sense. TSMC isn't getting any cheaper so penny pinching on mm2 is only going to get worse. Strix Point laptops are already expensive enough as it is.

We already have the L3 AIDA benchmark data. There's no decrease in bandwidth or latency compared to Z4.

 

[Goop_reformed]

Yep. Thing is, parameterization of stuff like that often costs more in dev/validation than you save in an incrementally smaller core variant. AMD has been wise to mostly avoid it thus far.

I think anyone believing that Strix Zen 5 will somehow be a materially worse microarchitecture than desktop Zen 5 is going to be disappointed.

What if the actual uplift is only +10%, that should satisfy both views

 

[csbin]

Yes, usually they design a core and that's what you get across the entire product stack. I think they only customised the FPU for PS5, but that's semi-custom business.

STX Z5/Z5C=FP 256
GNR Z5=FP 512