Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[Glo.]

total american cultural victory (he's polish but talks like a facebook Qmaga conspiraboomer).

Operation Mockingbird. Project that used over 400 journalists as an active assets of the CIA. Carl Bernstein exposed that at least 10 journalists and editors at the NYT were active CIA operatives.

You can google who Carl Bernstein is. I assume you won't because you know everything about the world.

 

[adroc_thurston]

Operation Mockingbird. Project that used over 400 journalists as an active assets of the CIA. Carl Bernstein exposed that at least 10 journalists and editors at the NYT were active CIA operatives.

You can google who Carl Bernstein is. I assume you won't because you know everything about the world.

total american cultural victory.
What's next, chemtrails?

 

[AMDK11]

This explains many things. I think 5 is the minimum. Most likely there will be a 6-way decoder. We'll see. There may be more GCC fixes coming soon.

 

[adroc_thurston]

This explains many things. I think 5 is the minimum. Most likely there will be a 6-way decoder. We'll see. There may be more GCC fixes coming soon.

Decode is frankly a not particularly super relevant point with AMD opcache sizes.
only people with terminal aarch64 brain poisoning focus on that.

 

[AMDK11]

So you think Zen 5 can still have a 4-way decoder?

 

[adroc_thurston]

So you think Zen 5 can still have a 4-way decoder?

i don't think anything.
It just doesn't matter much.

 

[gdansk]

This explains many things. I think 5 is the minimum. Most likely there will be a 6-way decoder. We'll see. There may be more GCC fixes coming soon.

It's 8 wide dispatch apparently. No idea what the decode width is. It could be like Zen 4 but with 6 wide decode instead of 4 wide decode and higher dispatch from micro-op cache.

https://twitter.com/x/status/1767222954465919460

 

[AMDK11]

If they add a wider decoder, I think it matters because it's not done without a reason.

Whether it matters more or less doesn't change the fact that I'm curious and would like to know. I think it's not just me.

 

[adroc_thurston]

If they add a wider decoder, I think it matters because it's not done without a reason.

many ways to skin that cat in particular.
You can always do the schizo move and add OoO decode capabilities (like what Atoms since Tremont do but crazier).

 

[Mahboi]

Meh.

 

[Hans Gruber]

I just want to point out that Arrow Lake is a truly new core for Intel on a brand new (20A) 5nm node. My concern is that Zen 5 will be on TSMC 5nm which they call 4nm because it's more advanced than N5 silicon. It trails TSMC 3nm in efficiency by 15-20%. Zen 5 was supposed to be on the 3nm silicon but TSMC has a shortage of 3nm or AMD elected to wait it out because they are cheap.

Alder Lake was a new Intel process. I know they like to call steps in their tick tock scheme new processes. Arrow Lake is a legit entirely new process. Alder Lake Intel made a huge IPC leap over Rocket Lake. I expect to see another big leap in IPC from Intel with Arrow Lake and a huge jump in efficiency because of the 20A node. I know they like to call it 2nm equivalent to TSMC silicon but it's a true 5nm process. Intel silicon is more dense than TSMC, some think that means better silicon.

Intel is going from 10nm silicon to 5nm (20A silicon with Arrow Lake. My concern for Zen 5 is that people think Intel is blowing smoke and ignoring the new process which brings a level playing field in core count potential as well as much better efficiency. The new 20A node may also provide an uplift in performance similar to what TSMC 7nm delivered for Zen 2.

That's why I said in previous posts that AMD should fast track Zen 5. AMD bumped the TDP of Zen 4 because they worried that Intel would wipe the floor with them. Intel has been selling space heaters disguised as CPU's for a long time. With 20A, that will no longer be the case. It just seems Intel takes two or three steps forward for every step or two AMD makes. Some people choose to ignore facts. Alder Lake was released on 10nm and that was the first Intel CPU on the new node. Everything before that for more than 6 years was on 14nm.

Intel has said they will have a process lead over TSMC with 18A.

AMD better make a strong showing with Zen 5. I think AMD really needs to be on 3nm for the sake of efficiency. I think a lot of people are hyping up Zen 5 without considering the silicon the processors will be sitting on. AMD has yet to show the ability to make a huge generational jump in IPC on the Ryzen platform. Zen 1 does not count because the processors before it were so bad. Zen 2 and Zen 3 were really good gains but Zen 4 was a disappointment. I personally think Intel will have at least a 20% IPC gain with Arrow Lake. AMD's core count advantage will be gone because Intel will be on 5nm silicon as well.

I do not think AMD will be in the rear view mirror of Intel. I do think AMD will end up far enough back where they cannot perform a pit maneuver on Intel. I guess we will find out by the end of the year

 

[adroc_thurston]

I just want to point out that Arrow Lake is a truly new core for Intel on a brand new (20A) 5nm node

yeah LNC sucks.
next.
also all Intel parts sans one irrelevant ARL-S tile are N3b.

It trails TSMC 3nm in efficiency by 15-20%.

no.

Zen 5 was supposed to be on the 3nm silicon but TSMC has a shortage of 3nm or AMD elected to wait it out because they are cheap.

has nothing to do with shortage and everything to do with N3b being bad.

I think AMD really needs to be on 3nm for the sake of efficiency

they do not.
and neither does Qualcomm.

 

[AMDK11]

They could achieve this by increasing the ability to send decoded microinstructions from memory, or by expanding the decoder from 4 to 6. Or both, by expanding the decoder to 5.

It will be interesting to see which option they chose by increasing shipping from 6 to 8.

 

[adroc_thurston]

by increasing the ability to send decoded microinstructions from memory

Their opcache is already the biggest and the widest in the industry.

or by expanding the decoder from 4 to 6. Or both, by expanding the decoder to 5.

Or you can have 2*4 or 2*6 stitching basic blocks.

 

[Mahboi]

AMD bumped the TDP of Zen 4 because they worried that Intel would wipe the floor with them.

 

[CouncilorIrissa]

AMD has yet to show the ability to make a huge generational jump in IPC on the Ryzen platform. Zen 1 does not count because the processors before it were so bad. Zen 2 and Zen 3 were really good gains but Zen 4 was a disappointment. I personally think Intel will have at least a 20% IPC gain with Arrow Lake. AMD's core count advantage will be gone because Intel will be on 5nm silicon as well.

I do not think AMD will be in the rear view mirror of Intel. I do think AMD will end up far enough back where they cannot perform a pit maneuver on Intel. I guess we will find out by the end of the year

It's Intel who need to show ability to produce meaningful IPC gains without going for more and more bloat.
GLC and Zen 4 shouldn't even be close on paper on most metrics.

 

[gdansk]

AMD has patents from years ago to do multiple fetch/decode/opcache units.

But could have been hedging their bets. Might need that at some point and patenting it just-in-case.

 

[PJVol]

total american cultural victory

Yeah, "total" is probably the only relevant word here, especially since 9/11 C.A.

 

[adroc_thurston]

It's Intel who need to show ability to produce meaningful IPC gains without going for more and more bloat.
GLC and Zen 4 shouldn't even be close on paper on most metrics.

well unfortunately LNC is more bloat and more cache for middling gains.

 

[Mahboi]

Intel really has entered the dying company cycle: "if I just push harder with the same thing that worked 10 years ago but absolutely doesn't work anymore, surely I'll get back to N°1"
Pat was supposed to save Intel's soul, not give the last rites.

 

[Hans Gruber]

View attachment 96441

I am talking out of the gate when Zen 4 was released. They added the eco mode later which was good. With power efficiency, Intel cannot touch AMD. That was the big selling point for AMD. If AMD was on N3P out of the gate with Zen 5. Things would be looking very good for AMD. N4 is behind in efficiency of the originally planned (Zen 5) N3 silicon. The good stuff is N3P. That gives an uplift in performance as well as nice efficiency gains over N3.

 

[Mahboi]

Eco mode existed even back in Zen 3. It was just never used since they were already full on efficient.

 

[Hans Gruber]

It's Intel who need to show ability to produce meaningful IPC gains without going for more and more bloat.
GLC and Zen 4 shouldn't even be close on paper on most metrics.

Alder Lake had a huge IPC gain. The 10nm silicon was holding back Intel. It was inferior to the 5nm TSMC silicon that Zen 4 was built on.

 

[adroc_thurston]

Alder Lake had a huge IPC gain.

19% is Zen3-size but at a huge bloatcost.

The 10nm silicon was holding back Intel.

no, their big cores are just bad.

It was inferior to the 5nm TSMC silicon that Zen 4 was built on.

i4 in MTL isn't yet the results.
Well you've seen the results.

 

[CouncilorIrissa]

Alder Lake had a huge IPC gain. The 10nm silicon was holding back Intel. It was inferior to the 5nm TSMC silicon that Zen 4 was built on.

Alder Lake had a similar IPC gain over SNC to than achieved by Zen 3 over Zen 2 by making everything bigger.
Zen 3 had the same gain over Zen 2 at the cost of 11% larger core IIRC.