Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[Abwx]

im still waiting for the low ballers to explain how from zen 1 to 4, core width didn't grow and OOOE window increased a small amount ( especially relative to others ) while doing ~ 50% more ipc and yet going to 6 wide plus a whole new fronted we know nothing about except its big shinny and new and we are getting -5 to 15% with clock regression.....

its not like there arent cores that size with that much more IPC on the market.

RGT is at it again these days, with the usual +30% IPC speculation of course but also no frequency regression this time, he even risk 6GHz as being possible...

 

[Fjodor2001]

Although he seemed to get the details about the Zen 5 delay right

How do we know if there has been any delay, when no official release date has ever been communicated?

Could be that whatever the release date finally is communicated as was what AMD was targetting from the start anyway.

 

[Timorous]

pffft... this is not an Intel thread... 😛

Indeed, no more hype(r)threads for Intel cpus anymore.

 

[Kepler_L2]

I’ve had more than 1 person tell me that CB R23 1T is >=2800 which is a >=40% increase. If I had to take a geomean of Zen 5 leakers it’d probably be a 40% 1T perf increase overall.

I don’t personally believe that but it’s at least consistent. The only person saying it’s not hype™ is MLID who’s track record is spotty. Although he seemed to get the details about the Zen 5 delay and 800 series chipset right .. so ymmv.

That was on A0 silicon which had a clock regression 😛

 

[igor_kavinski]

So things looking great for Zen 5 but AMD decided to take some extra time to iron out all the kinks, have a stable BIOS at launch with decent RAM speeds and may even launch X3D simultaneously coz by then they would have built enough stock already.

 

[FlameTail]

Can we do a microarchitecture comparison of Zen 4, Raptor Cove(or RWC), M3 P-core and Cortex X4?

Decoder Width
Dispatch width
ROB size
Etc...

 

[igor_kavinski]

Zen 4 4-wide
RPC 5-wide
RWC 6-wide (re-compiled software could theoretically run faster than Raptor Lake Refresh)

Source for above 3 is ChatGPT (please correct if it spitted out misinformation)

M3 width probably no one knows. M1 is supposed to be 8-wide according to this: https://news.ycombinator.com/item?id=25394447
X4 10-wide (yowza!)
Zen 5 possibly 8-wide

Wow. Looks like ARM is shooting for the moon.

 

[CouncilorIrissa]

There’s a great uarch cheat sheet for all of you nerds:

Cardyak’s Microarchitecture Cheat Sheet

docs.google.com

A17P is 9-wide according to this.

 

[FlameTail]

A17P is 9-wide according to this.

Yes. In the A17/M3, the decider got upped from 8 to 9 wide.

 

[FlameTail]

Cardyak’s Microarchitecture Cheat Sheet

docs.google.com

Now, that's the good stuff

 

[CouncilorIrissa]

Zen 4 4-wide
RPC 5-wide
RWC 6-wide (re-compiled software could theoretically run faster than Raptor Lake Refresh)

Source for above 3 is ChatGPT (please correct if it spitted out misinformation)

M3 width probably no one knows. M1 is supposed to be 8-wide according to this: https://news.ycombinator.com/item?id=25394447
X4 10-wide (yowza!)
Zen 5 possibly 8-wide

Wow. Looks like ARM is shooting for the moon.

Intel's P-cores have been 6-wide since GLC.

edit: there's also a uarch block diagram repo: https://drive.google.com/drive/u/0/folders/1W4CIRKtNML74BKjSbXerRsIzAUk3ppSG

 

[FlameTail]

Wow. Looks like ARM is shooting for the moon.

SuperWide UltraEfficient

 

[FlameTail]

Zen has been 4 wide/6 dispatch all the way from Zen 1 to Zen 4?

That is crazy.

 

[CouncilorIrissa]

Zen has been 4 wide/6 dispatch all the way from Zen 1 to Zen 4?

That is crazy.

Yeah, from numbers alone you'd think GLC+ onward cores belong to a different weight class.

 

[majord]

I think you need to look back at Excavator's front end , including op cache , before being too surprised at Zen's current IPC despite only 4 decoders. Pushing any more IPC out of it , i.e Zen 5, without going wider? , yeah that will start to get interesting.

 

[StefanR5R]

Can we do a microarchitecture comparison of Zen 4, Raptor Cove(or RWC), M3 P-core and Cortex X4?

Ever noticed the POST THREAD button at the top right of each subforum page?

 

[Glo.]

There’s a great uarch cheat sheet for all of you nerds:

Cardyak’s Microarchitecture Cheat Sheet

docs.google.com

A17P is 9-wide according to this.

Thanks.

I started to believe that 30% IPC uplift for Zen 5, suddenly. A lot of room for improvement of the core itself, its not even funny.

 

[CouncilorIrissa]

Ever noticed the POST THREAD button at the top right of each subforum page?

Good luck entering such a thread without wearing a hazmat suit.

 

[AMDK11]

Zen 4 4-wide
RPC 5-wide
RWC 6-wide (re-compiled software could theoretically run faster than Raptor Lake Refresh)

Source for above 3 is ChatGPT (please correct if it spitted out misinformation)

M3 width probably no one knows. M1 is supposed to be 8-wide according to this: https://news.ycombinator.com/item?id=25394447
X4 10-wide (yowza!)
Zen 5 possibly 8-wide

Wow. Looks like ARM is shooting for the moon.

Zen1-Zen4 4-way x86 decoder

Conroe(Core 2) - SunnyCove/CypressCove 4-way x86 dekoder(1+3)

GoldenCove - RedwoodCove 6-way x86 dekoder(6(1+5(?)))

 

[FlameTail]

Zen1-Zen4 4-way x86 decoder

Conroe(Core 2) - SunnyCove/CypressCove 4-way x86 dekoder(1+3)

GoldenCove - RedwoodCove 6-way x86 dekoder(6(1+5(?)))

What does 1+3 / 1+5 mean?

Also why specify it's an x86 decoder? We know it's an x86 core.

 

[Saylick]

What does 1+3 / 1+5 mean?

Also why specify it's an x86 decoder? We know it's an x86 core.

Complex vs simple decoder. Intel traditionally has one complex with the rest simple.

 

[FlameTail]

Complex vs simple decoder. Intel traditionally has one complex with the rest simple.

Ooh. Is Intel the only one doing this?

 

[igor_kavinski]

Ooh. Is Intel the only one doing this?

ARM vs x86: Which architecture owns the future?

Deciding between ARM vs. x86 for your use case? Explore differences in performance, software compatibility, sales volume & cost for your business devices.

emteria.com

RISC has far fewer instructions than CISC, and each basic instruction is executed in a single clock cycle. CISC's instructions can be complex and perform multiple tasks in a single instruction. CISC's complex instruction set makes x86 chips harder to design because the chip has to be able to account for the complex instructions, making x86 chips typically more expensive.
Because RISC uses simple instructions and tends to use less power per instruction, this makes ARM chips ideal for devices that need longer battery life.

So all x86 CPUs should have at least one complex decoder. ARM doesn't need one.

 

[JustViewing]

In AMD terms,
Dispatch = Macro Ops,

For Zen4, in theory for 6 Dispatches there can be up to 12 micro ops.

Zen4 can have peek execution of 14 micro ops. It won't be sustainable of course, bottle necked by front and back end. In addition to this, few instructions can be resolved within scheduler like mov reg,reg, load imm etc.

 

[Tuna-Fish]

Zen has been 4 wide/6 dispatch all the way from Zen 1 to Zen 4?

That is crazy.

Zen is wider than 4 if you run from the uop cache. The cache can deliver up to 9 uops per clock, but alignment restrictions reduce average throughput. The pipeline after that (crucially, rename) is 6 wide.

Ooh. Is Intel the only one doing this?

I think AMD decoders are more flexible, but this is really not something that actually matters much. As a rule, complex ops are slow and if you have plenty of them you are not going to be limited by decode anyway.