Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[adroc_thurston]

An architectural change that increases IPC may or may not increase power consumption

It always does.
The old Intel rule of the 00s was 2% IPC for each 1% of power spent.

but my God did it take a whole bunch of useless posts and repetitions to get to that point

Not my fault you're not very smart and haven't touched a server part in your life.

 

[Schmide]

Not my fault you're not very smart.

Actually it is. Giving, while technically correct, answers without showing the work or source makes everyone less smart.

 

[adroc_thurston]

Giving, while technically correct, answers without showing the work or source makes everyone less smart.

Yeah but Milan benches are all over the internet, including Anandtech.
I don't have to spoonfeed anyone, period.

 

[HurleyBird]

It always does.

Thank you for confirming that whatever you are, you aren't an engineer.

 

[Abwx]

The old Intel rule of the 00s was 2% IPC for each 1% of power spent.

One can hardly check if this rule is accurate because there s often node shrinks that blur the comparison, so far Intel s Haswell increased IPC substancially relatively to Ivy Bridge.

Since they were both 22nm fabbed IB ended with better perf/watt than HW, as a result HW didnt sell well in servers markets with users skipping it in the waiting of the next uarch wich would benefit from a node shrink at 14nm.

 

[HurleyBird]

One can hardly check if this rule is accurate because there s often node shrinks that blur the comparison, so far Intel s Haswell increased IPC substancially relatively to Ivy Bridge.

Also doesn't disprove that there are instances where a change can both increase IPC and reduce power consumption, which is very obviously true. Practically anything that reduces the need to move up the memory hierarchy may do that, or anything that reduces communication distances/hops, and of course not all work is created equal and it's possible to do more or less work to achieve a result. A more general approach to finding a result can both perform worse and consume more energy than a more specific approach. It's of course possible to do more work with less active transistors and vice versa. And then there's pipelines, branch prediction (which is huge, mispredictions are extremely expensive), OoO etc.

It's not a claim any engineer would make.

 

[Abwx]

Also doesn't disprove that there are instances where a change can both increase IPC and reduce power consumption, which is very obviously true. Practically anything that reduces the need to move up the memory hierarchy may do that, or anything that reduces communication distances/hops, and of course not all work is created equal and it's possible to do more or less work to achieve a result. A more general approach to finding a result can both perform worse and consume more energy than a more specific approach. It's of course possible to do more work with less active transistors and vice versa. And then there's pipelines, branch prediction (which is huge, mispredictions are extremely expensive), OoO etc.

It's not a claim any engineer would make.

So far i ve seen no numbers that would point to better efficency with higher IPC, Zen 3 indeed has better efficency than Zen 2 but i suspect that they used an improved 7nm process going from vanilla N7 to N7P.

FI a misprediction will stall the pipeline and as a consequence there s no computation that is done in the back end, hence it doesnt use as much power as when the pipeline is correctly filled and exe units are performing actual work.

 

[Mopetar]

Likelihood of increasing IPC while decreasing power is low. Not because it's impossible, but because it implies the previous approach was less efficient and used more transistors to achieve that worse result.

There's not many places in a modern CPU where you could expect to swap out hardware for asymptotically better performance while reducing the transistors used at the same time. That fruit was picked a long time ago.

Almost anything the reduces memory latency (at least in terms of raw cycle count since the access time may decrease just as clock speed increases, which keeps the ratio similar even if both are faster) is a result of adding extra cache, which requires more transistors. Those need more power, but if they keep the rest of the CPU better fed it might reduce the overall power used for some workload even though the CPU is using more power at any individual point in time during that point.

If we froze our process tech and it never improved, newer chips would see a gradual increase in power use. The efficiency for some workloads may improve as the extra transistors allow that work to finish faster than the extra power increase accumulates to surpass the previous energy total.

Perhaps in the long run being stuck in that situation would drive engineers to rework existing solutions to use less power, even if only because there's no additional room to increase the power or add transistors. But generally, it's been node shrinks reducing both capacitance and voltage required that has led to lower power requirements.

 

[Doug S]

I don’t think that’s it. Zen 5 shouldn’t be that much more expensive than Zen 4.

Price has only a loose relationship with cost. If Zen 5 is significantly better than Zen 4 as well Intel's offerings, AMD will be able to charge more for it. Those hoping for massive increases in Zen 5 performance should realize that will mean increases in Zen 5's price, at least for the higher bin parts.

 

[coercitiv]

Likelihood of increasing IPC while decreasing power is low.

Zen 3 vs. Zen 2

• 19% IPC increase
• same node class, but improved
• slightly higher clocks
• bigger die
• ISO power
• right in our face

Spoiler

The biggest problem in this thread isn't this discussion point though, but rather whether folks around here are going to accept the rude verdicts of a poster as gospel or demand the minimum of proof and decorum.

 

[HurleyBird]

FI a misprediction will stall the pipeline and as a consequence there s no computation that is done in the back end, hence it doesnt use as much power as when the pipeline is correctly filled and exe units are performing actual work.

This is true of course, but you also use more energy on the frontend, you can create cache pollution, etc. Didn't mean to imply that a cache miss will always reduce instant power consumption, just that there could be some scenarios, if not on the prediction side then the speculative execution side. Instant power consumption isn't really something people think of that much compared to task energy.

The better proof is on the cache side.

Likelihood of increasing IPC while decreasing power is low. Not because it's impossible, but because it implies the previous approach was less efficient and used more transistors to achieve that worse result.

There's not many places in a modern CPU where you could expect to swap out hardware for asymptotically better performance while reducing the transistors used at the same time. That fruit was picked a long time ago.

There's also area to consider rather than just active transistors.

I somewhat agree on the low hanging fruit part. In terms of the most fundamental aspects, yeah, not much at least that our human faculties can observe... probably.

In terms of more derived aspects, AMD leaves low hanging fruit all the time, for example, for the sake of agility. Zen2 with it's dual CCXes, Zen4c with that plus a total lack of optimization for its target frequency while retaining many disadvantages of a more speed-demon focused architecture, etc.

I'm also not sure we've seen the last Core2 moment, Maxwell moment, etc. Before those monumental leaps forward, it also didn't seem like there was that much room left for fundamental improvements. Maxwell especially was less transistors for more frequency and performance (and better performance/flop) at substantially less power on the same node despite being clearly derived from Kepler, which shows that Kepler had a lot of fruit to pick despite seeming advanced at the time.

Almost anything the reduces memory latency (at least in terms of raw cycle count since the access time may decrease just as clock speed increases, which keeps the ratio similar even if both are faster) is a result of adding extra cache, which requires more transistors. Those need more power, but if they keep the rest of the CPU better fed it might reduce the overall power used for some workload even though the CPU is using more power at any individual point in time during that point.

I would assume the extra transistors for cache usually consume less, but there's also elements of cache size versus timing (Apple gets the best of both worlds with its L1), and organization. Zen2->Zen3 going from 2 CCX's per CCD to 1 didn't need to grow the cache physically.

If we froze our process tech and it never improved, newer chips would see a gradual increase in power use. The efficiency for some workloads may improve as the extra transistors allow that work to finish faster than the extra power increase accumulates to surpass the previous energy total.

Perhaps in the long run being stuck in that situation would drive engineers to rework existing solutions to use less power, even if only because there's no additional room to increase the power or add transistors. But generally, it's been node shrinks reducing both capacitance and voltage required that has led to lower power requirements.

I think you might see a few cycles like that. Reducing voltage wouldn't stop being a focus right away. There would be some space to take a break from constant shrinkage and optimize for the "final node." What happens next also depends on whether that process becomes increasingly economical or not.

 

[Fjodor2001]

Here's what my inside sources tell me for Zen5:

* 5-35% IPC increase
* -5% to 15% frequency increase
* Max core count: 8-32P + possibly 8-32E cores
* Price of top AM5 desktop SKU: $499-$1599
* IO-die: Possibly same, possibly with e.g. RDNA 3.5+.
* Chipset: Possibly same or maybe e.g. node improvement.
* Release date: 2024Q1 -- 2025.

All from inside sources at AMD. Please feel free to call me out at end of 2025 if any of the above turns out to be inaccurate. 😎

 

[APU_Fusion]

Here's what my inside sources tell me for Zen5:

* 5-35% IPC increase
* -5% to 15% frequency increase
* Max core count: 8-32P + possibly 8-32E cores
* Price of top AM5 desktop SKU: $499-$1599
* IO-die: Possibly same, possibly with e.g. RDNA 3.5+.
* Chipset: Possibly same or maybe e.g. node improvement.
* Release date: 2024Q1 -- 2025.

All from inside sources at AMD. Please feel free to call be out at end of 2025 if any of the above turns out to be inaccurate. 😎

You are obviously misinformed because you missed it will have either SMT2 or SMT 4 😎

 

[Timorous]

Here's what my inside sources tell me for Zen5:

* 5-35% IPC increase
* -5% to 15% frequency increase
* Max core count: 8-32P + possibly 8-32E cores
* Price of top AM5 desktop SKU: $499-$1599
* IO-die: Possibly same, possibly with e.g. RDNA 3.5+.
* Chipset: Possibly same or maybe e.g. node improvement.
* Release date: 2024Q1 -- 2025.

All from inside sources at AMD. Please feel free to call be out at end of 2025 if any of the above turns out to be inaccurate. 😎

Hi Paul.

Now all we need is someone to extrapolate the nT cinebench scorer for a 35% IPC gain with a 15% clock increase and an increase to 32 cores.

 

[Fjodor2001]

Hi Paul.

Now all we need is someone to extrapolate the nT cinebench scorer for a 35% IPC gain with a 15% clock increase and an increase to 32 cores.

That's too low. Max core count would be 32P+32E. 😛

But we could also have a disaster and get 16C, -5% frequency, 5% IPC, $1599, same IO die and chipset as for Zen4, in 2025Q4.

Just summarizing all the possible options gathered throughout this thread.

 

[Abwx]

Here's what my inside sources tell me for Zen5:

* 5-35% IPC increase
* -5% to 15% frequency increase
* Max core count: 8-32P + possibly 8-32E cores
* Price of top AM5 desktop SKU: $499-$1599
* IO-die: Possibly same, possibly with e.g. RDNA 3.5+.
* Chipset: Possibly same or maybe e.g. node improvement.
* Release date: 2024Q1 -- 2025.

All from inside sources at AMD. Please feel free to call be out at end of 2025 if any of the above turns out to be inaccurate. 😎

MLID, is that you.??....

 

[igor_kavinski]

Just summarizing all the possible options gathered throughout this thread.

You forgot multiple CCDs stacked on top of each other. Yes, AM4 cooler compatibility will be compromised but AMD is really scared of Intel Beast Lake 😛

They have no choice but to do minimum dual stacked 4 CCD design with 32 fat cores to have any chance of countering the 40 core Intel Beast. 64 virtual cores should let them match or slightly beat the HT-castrated 40 P-cores of Beast Lake. AMD had to pull all the tricks up their sleeves to keep themselves afloat. They never thought Intel would do something so insane.

 

[Thibsie]

Laugh as long as you want but for now I'm not sure who's the fool right now.

 

[igor_kavinski]

You are obviously misinformed because you missed it will have either SMT2 or SMT 4 😎

SMT3 coz Primes are better.

 

[igor_kavinski]

All from inside sources at AMD.

Yeah, their janitors...

 

[linkgoron]

SMT3 coz Primes are better.

2 is a prime

 

[Kaffeekenan]

SMT3 coz Primes are better.

2 is a prime...

 

[igor_kavinski]

2 is a prime

2 is a prime...

But we already got SMT2 in our CPUs. Next up is SMT3. SMT4 would be too expensive to implement.

 

[Saylick]

But we already got SMT2 in our CPUs. Next up is SMT3. SMT4 would be too expensive to implement.

Nah, SMT>1 is old tech. Where's reverse SMT when you need it??

 

[Goop_reformed]

That's too low. Max core count would be 32P+32E. 😛

But we could also have a disaster and get 16C, -5% frequency, 5% IPC, $1599, same IO die and chipset as for Zen4, in 2025Q4.

Just summarizing all the possible options gathered throughout this thread.

To be honest I'm sort of baffled of how people here treated mlid like he's an anti-christ. He definitely has good infos and people who are into tech news watch him religiously. Right after a new video is posted, a member linked that here almost instantly. I used to think people hate watch him but my opinions have been swayed.