Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[Hans Gruber]

You're talking about what Geppetto from amd said, aka the bald twat who later resigned. I remember such a statement but it was about getting out of 1:1 ram sync for the fclk and if. 8000 takes it out of it as I understand. the benefits are minimal compared to an intel ks processor capable of hitting high 7000 or low 8000 oc compared to 6400.

ditto on the latency. all the best kits right now have a 10ns latency. The best ddr4 was around 9ns or 8.5 ns latency. still nice to see ddr5 prices so cheap compared to this time last year.

Add to the future problems AMD faces with Intel's 5 nodes in 4 years thing. The Raptor Lake refresh arrives in October. This will further distance Intel from Zen 4. By the time Arrow Lake is released in 2024. The process advantage AMD had or will have based on efficiency, will be lost. The Arrow Lake CPU's will have an equal number (P cores equal to or greater than AMD cores) of P cores and a ton of E cores. 20A is a 5nm process. Intel's silicon is more dense than TSMC. They are more robust. I do not care about the propaganda of Intel. Saying that 5nm Intel is equal to 2 or 3nm TSMC silicon. The point is that 5nm Intel silicon will have the power efficiency that Intel lacked in current and previous generations vs. AMD. I still think AMD will have a power efficiency advantage with Zen 5.

The Intel roadmap indicates they think Intel will have full leadership when the Lunar Lake 18A process comes to market. That means Intel CPU's will be the class leader in every aspect. Core count, power efficiency, frequency (mhz) and IPC.

 

[jpiniero]

I have bad news for you since Dense CCD is only weeks after normal CCD and it's on N3e.
Please stop talking about things you have no idea of.

That would mean it would be one of the first products using N3E. Which seems tough to believe.

 

[adroc_thurston]

That would mean it would be one of the first products using N3E

Yea, not news.

Which seems tough to believe.

Why?
AMD is the sole user of SoIC-X for many years to come.
lol

 

[jpiniero]

Yea, not news.

Why?
AMD is the sole user of SoIC-X for many years to come.
lol

It's been a really long time since AMD has been an early adopter of a TSMC node. Really anyone other than Apple.

 

[adroc_thurston]

It's been a really long time since anyone other than Apple has been an early adopter of a TSMC node.

Everyone wants to get early dibs on Turin-D (it's the best!).
What is even special about this all.
Apple is of no relevance anymore ever since they cut current year SoCs from mainstream iPhones, thus cutting wafer volume at ramp by a lot.

 

[jpiniero]

Apple is of no relevance anymore ever since they cut current year SoCs from mainstream iPhones, thus cutting wafer volume at ramp by a lot.

That's because N3B is a terrible value compared to N4P.

Apple did it last year too (only the Pro models got the A16)

 

[adroc_thurston]

That's because N3B is a terrible value compared to N4P.

N5p isn't terrible value but A16 is 14 pro/max only.
So it's intentional segmentation strategy due to rising SoC costs.
So yes, Apple will no longer ramp anywhere near the amount of wafers on new nodes as they did usually.

 

[jpiniero]

So it's intentional segmentation strategy due to rising SoC costs.

That too.

 

[Markfw]

Add to the future problems AMD faces with Intel's 5 nodes in 4 years thing. The Raptor Lake refresh arrives in October. This will further distance Intel from Zen 4. By the time Arrow Lake is released in 2024. The process advantage AMD had or will have based on efficiency, will be lost. The Arrow Lake CPU's will have an equal number (P cores equal to or greater than AMD cores) of P cores and a ton of E cores. 20A is a 5nm process. Intel's silicon is more dense than TSMC. They are more robust. I do not care about the propaganda of Intel. Saying that 5nm Intel is equal to 2 or 3nm TSMC silicon. The point is that 5nm Intel silicon will have the power efficiency that Intel lacked in current and previous generations vs. AMD. I still think AMD will have a power efficiency advantage with Zen 5.

The Intel roadmap indicates they think Intel will have full leadership when the Lunar Lake 18A process comes to market. That means Intel CPU's will be the class leader in every aspect. Core count, power efficiency, frequency (mhz) and IPC.

Zen 4, especially server (Genoa) is so far ahead of Intel that 2-3 of their nodes will just get them close, and AMD is not standing still. I would leave your flag waving alone until Intel actually takes a lead in ANYTHING.

And this is a Zen 5 thread, not an Intel thread.

 

[A///]

Add to the future problems AMD faces with Intel's 5 nodes in 4 years thing.

Intel claims they will but haven't shown any result through hvm they can accomplish this. this is also the same intel that said they'd have 10nm available soon several years before they began the lead process into achieving that goal, which as you know they failed miserably at.

The Raptor Lake refresh arrives in October. This will further distance Intel from Zen 4.

that's fantastic, the zen 4 processors won't burn up as a result of how hot the refresh is. latest reports show an avg 20% gain in some scenarios with a 13% or more increase in power usage.

By the time Arrow Lake is released in 2024. The process advantage AMD had or will have based on efficiency, will be lost.

Almost 2+ quarters after amd is allegedly releasing their zen 5 processors?

The Arrow Lake CPU's will have an equal number (P cores equal to or greater than AMD cores) of P cores and a ton of E cores.

Can you provide a source that can confidently state that arl will have 16 p-cores? I can't find such a source. All sources lead back to the initial rumors long ago of a 8+32 solution or 8+24 solution. Intel as it stands now needs 24 cores at the top to match or slightly edge out a 16 core ryzen processor, including at least 50-75 watts extra power. The refresh is nothing more than a 200 mhz bump and increased power usage.

20A is a 5nm process. Intel's silicon is more dense than TSMC. They are more robust. I do not care about the propaganda of Intel.

that's all great but if the design sucks the design sucks. Intel will go on a tiled approach comprised of various nodes. the compute tiles will be at that. there is no gaurantee their new design process will work out well compared to a more traditional design. So far their hybrid system hasn't put a large or even minor gap between it and zen. the overall complexity of intel's approach and costs scope creep is going to be higher than it is for amd.

The point is that 5nm Intel silicon will have the power efficiency that Intel lacked in current and previous generations vs. AMD. I still think AMD will have a power efficiency advantage with Zen 5.

and you come down to earth here with sensibility between your ears.

The Intel roadmap indicates they think Intel will have full leadership when the Lunar Lake 18A process comes to market. That means Intel CPU's will be the class leader in every aspect. Core count, power efficiency, frequency (mhz) and IPC.

Intel saying and thinking about things while not having accomplished 1/8th of their approach and future plans is fruitless to repeat online by you or anyone for that matter.

 

[A///]

Zen 4, especially server (Genoa) is so far ahead of Intel that 2-3 of their nodes will just get them close, and AMD is not standing still. I would leave your flag waving alone until Intel actually takes a lead in ANYTHING.

And this is a Zen 5 thread, not an Intel thread.

This a much nicer way of saying what I originally planned on telling him but removed last minute out of courtesy. It involves speech and one's posterior. As you point out they'll continuously play the catch up game. Soon we'll be blaming them for global warming and rising water levels and not vehicles.

 

[Joe NYC]

I have bad news for you since Dense CCD is only weeks after normal CCD and it's on N3e.
Please stop talking about things you have no idea of.

Is it a race now between Sierra Forrest and Turin Dense?

Sierra Forrest will have hard time competing with Bergamo. It will be hopeless against Turin Dense...

 

[Joe NYC]

Yea, not news.

Why?
AMD is the sole user of SoIC-X for many years to come.
lol

I was wondering about that. One rumor was that AMD bought out all of the capacity for years to come.

Or is there any kind of exclusivity agreement in addition to that?

As I said in another thread, AMD also has incentives to keep this partnership going it trying to bring to high volume manufacturing higher levels of stacking.

https://twitter.com/x/status/1402804961440780291

 

[adroc_thurston]

Is it a race now between Sierra Forrest and Turin Dense?

Not really, SRF is a joke in everything not upfront costs (Intel sells it for pennies).

It will be hopeless against Turin Dense...

Hyperscalers think as much yes.

One rumor was that AMD bought out all of the capacity for years to come.

Yea.

Or is there any kind of exclusivity agreement in addition to that?

No, 3D is hard and no one else is really willing.

 

[maddie]

AMD also has incentives to keep this partnership going it trying to bring to high volume manufacturing higher levels of stacking

Partnership is right as AMD must be doing a lot of the R&D for this. It's as much theirs as TSMC.

 

[Joe NYC]

Partnership is right as AMD must be doing a lot of the R&D for this. It's as much theirs as TSMC.

And for TSMC, the benefits start to multiply (rather than just add) with higher levels of stacking.

Let's say selling 2 wafers or 4 wafers instead of one in 2 or 4 layers of stacking. And TSMC could also perfect Wafer on Wafer stacking for this application. So TSMC is strongly incentivized to continue on this research to bring it to high volume manufacturing.

We just don't know how challenging it is...

 

[adroc_thurston]

We just don't know how challenging it is...

The main challenge with HB is HB itself being a rather slow process for CoW purposes.
Which is why SoIC-P is a thing for mainstream applications.

 

[Joe NYC]

The main challenge with HB is HB itself being a rather slow process for CoW purposes.
Which is why SoIC-P is a thing for mainstream applications.

That part makes sense, that CoW is an elaborate process, one at the time.

But to get higher levels of stacking, TSMC would use WoW stacking is fast. It can stack > 1,000 dies all at once on the Wafer. Which is where TSMC wants to be.

Before the tech recession, as late as early 2022, TSMC was going to build another giant N7 fab (which subsequently got scaled back or repurposed). IMO, TSMC believes that N7 demand will continue to be strong or even increase - and stacking applications may be one of the main uses...

 

[Joe NYC]

The main challenge with HB is HB itself being a rather slow process for CoW purposes.
Which is why SoIC-P is a thing for mainstream applications.

SoIC-P (bumped) vs. SoIC-X (bumpless) is lame.

 

[adroc_thurston]

But to get higher levels of stacking, TSMC would use WoW stacking is fast

WoW is of very limited use.

SoIC-P (bumped) vs. SoIC-X (bumpless) is lame.

It's good, poverty segments don't need hybrid bonding and -P shares the process flow with CoWoS-S that way.

 

[Ajay]

TSMC is building a new factory for advanced packaging - as the writing is on the wall.

Driven by AI boom, TSMC to invest $2.9 billion in advanced chip plant in Taiwan

Driven by a surge in demand for artificial intelligence, Taiwanese chip maker TSMC plans to invest nearly T$90 billion ($2.87 billion) in an advanced packaging facility in northern Taiwan, the company said on Tuesday.

www.reuters.com

 

[maddie]

The main challenge with HB is HB itself being a rather slow process for CoW purposes.
Which is why SoIC-P is a thing for mainstream applications.

Any info on throughput?

 

[adroc_thurston]

Any info on throughput?

I don't think it's public so not sure if I should talk about it here.
But it's kinda slow.
Not backbreakingly so but not quite suitable for mainstream yet.

 

[Joe NYC]

Any info on throughput?

We can go with the assumption that AMD is using all of it and there is no extra capacity to spare.

So that's the sum of:
- 5800x3d, 5600x3d
- Milan X
- 7800x3d etc
- Genoa X

Still on the way:
- Mi300

We will know that capacity caught up and is exceeding demand for these parts when AMD introduces 7600x3d.

 

[adroc_thurston]

when AMD introduces 7600x3d.

They won't, you're going straight to Granite Ridge.