Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[blackangus]

What I mean is that Macs are still considered the go to solution for work.

Not really most of the large businesses (fortune 500 companies) I know do not provide macs for workers.
In some verticals yes, but that is a very small amount from what I have seen.

 

[DisEnchantment]

Me and @BorisTheBlade82 been discussing advanced packaging and disaggregation for AMD Mobile SoCs for quite a while but seems each year it is still one generation away.
What is the consensus with Mobile SoC disaggregation for AMD. Is it Strix or Strix successor?
Or there is no Strix Successor, just Medusa for both DT and Mobile?

SoC tile with DDR5 MC like MTL + Memory Attached LLC on N6+ would really take integrated graphics to the next level.
RDNA4 also seems to rely heavily on MALL as can be seen from the LLVM MRs.

 

[Philste]

LNL just won't have the power available to be competitive against Strix Halo since it's geared more towards low power laptops with all day battery life.

I was talking about normal Strix, not Halo. I mean what's the point of Strix when iGPU isn't better in games because of bandwidth Limit? You will have a CPU that destroys everything in Cinebench, but who needs that in a Laptop? AIE is also stronger but for 98% of consumers strix would be totally unnecessary compared to Pheonix or even Rembrandt.

Most useful upgrades that x86 Laptop CPUs need right now is Battery Life in surf/Video scenarios and iGPU Power. Will Strix bring anything meaningful here? From the Informations we got now, I would say no. It will have a beast of a CPU and NPU. But Lunar Lake will also have the latter, probably a competitive iGPU, and it has the potential to fix MTLs flaws, with putting the LPE-Cores on the Compute Tile. Sure, it's CPU gets trashed by Strix, probably by 100%. But who needs this perfomance in slim devices?

This doesn't mean Strix won't be an impressive product, but I kinda think AMD misses the point of a mobile CPU with it. The biggest upgrade seems to be in the parts where an upgrade isn't really needed.

 

[Glo.]

Then what is purpose of Radeon 880M?
To be even more limited by memory bandwidth?

Yes.

 

[igor_kavinski]

That's actually how much my boss makes and I starve in comparison, with crappy health insurance and not enough to get my own apartment with a proper lease agreement.

And oh, you should watch him type a formula in Excel. You will want to kill yourself.

 

[moinmoin]

Me and @BorisTheBlade82 been discussing advanced packaging and disaggregation for AMD Mobile SoCs for quite a while but seems each year it is still one generation away.
What is the consensus with Mobile SoC disaggregation for AMD. Is it Strix or Strix successor?
Or there is no Strix Successor, just Medusa for both DT and Mobile?

SoC tile with DDR5 MC like MTL + Memory Attached LLC on N6+ would really take integrated graphics to the next level.
RDNA4 also seems to rely heavily on MALL as can be seen from the LLVM MRs.

Strix Halo supposedly will be disaggregated and have the Zen 5 gen's peak high tech packaging. No actual details publicly known though.

 

[jpiniero]

Strix Halo supposedly will be disaggregated and have the Zen 5 gen's peak high tech packaging. No actual details publicly known though.

I've been under the impression that Strix Halo is just Fire Range with a different IO die and packaging so that it has the 256-bit memory.

 

[Philste]

I've been under the impression that Strix Halo is just Fire Range with a different IO die and packaging so that it has the 256-bit memory.

From what I understand it was rumored to have it's own CCDs with only 16MB L3. Sounds really unlikely, but if it is true it's just a sign of how expensive it will be. Every die would be an exclusive tapeout only for this one product, quite contrary to what AMD is trying to do with their chiplets so far.

 

[FlameTail]

depends on LPDDR clocks. 8840HS can run at 7500 MT/s, if Strix can run LPDDR memory at ~10000, it's gonna be fine

No LPDDR in the market can reach 10000

Fastest is LPDDR5T/X-9600

But the availability of this is limited, even in flagship Android phones today.

So I expect STX will max out at LPDDR5X-9600

 

[aigomorla]

Only wall of text i should be seeing is Zen5 in this thread.
I shouldn't be seeing Apple.
If you want to talk about Apple, there is a perfectly good apple thread.
But this is reserved for Zen5 and only Zen5.

Moderator Aigo

 

[Markfw]

Only wall of text i should be seeing is Zen5 in this thread.
I shouldn't be seeing Apple.
If you want to talk about Apple, there is a perfectly good apple thread.
But this is reserved for Zen5 and only Zen5.

Moderator Aigo

Isn't strix and strix halo Zen 5 ? I could be wrong, not questioning you, just asking. Is the below what they are talking about ? (STRIX POINT ??) the same ?

 

[Kepler_L2]

Me and @BorisTheBlade82 been discussing advanced packaging and disaggregation for AMD Mobile SoCs for quite a while but seems each year it is still one generation away.
What is the consensus with Mobile SoC disaggregation for AMD. Is it Strix or Strix successor?
Or there is no Strix Successor, just Medusa for both DT and Mobile?

SoC tile with DDR5 MC like MTL + Memory Attached LLC on N6+ would really take integrated graphics to the next level.
RDNA4 also seems to rely heavily on MALL as can be seen from the LLVM MRs.

Strix Halo is already using chiplets, and I believe most of the Medusa lineup does too.

 

[BorisTheBlade82]

From what I understand it was rumored to have it's own CCDs with only 16MB L3. Sounds really unlikely, but if it is true it's just a sign of how expensive it will be. Every die would be an exclusive tapeout only for this one product, quite contrary to what AMD is trying to do with their chiplets so far.

I could imagine AMD to follow the blueprint of MI300A. It was pretty surprising for me that they already included alternative D2D interfaces in the Zen4 CCD for which they basically just needed some different metal layers in order to enable them.
The question for me is if they could use InFO-RDL or if they rely on capacity constrained CoWoS.

 

[Nothingness]

- Oops missed moderator message about Apple..

 

[FlameTail]

I could imagine AMD to follow the blueprint of MI300A. It was pretty surprising for me that they already included alternative D2D interfaces in the Zen4 CCD for which they basically just needed some different metal layers in order to enable them.
The question for me is if they could use InFO-RDL or if they rely on capacity constrained CoWoS.

How much die area do those D2D interfaces take?

 

[SteinFG]

The question for me is if they could use InFO-RDL or if they rely on capacity constrained CoWoS.

Curently it's believed to use the same RDL tech that Navi 31/32 uses

 

[BorisTheBlade82]

How much die area do those D2D interfaces take?

They are tiny, which absolutely makes sense when you think about how much denser SoIC is than having to contact IFoP.
Need to search for the annotated die shot I saw.

 

[BorisTheBlade82]

How much die area do those D2D interfaces take?

Found it. Official slide from AMD. Look at the tiny blue squares compared to the GMI links.

Curently it's believed to use the same RDL tech that Navi 31/32 uses

Hoping this as well. That would mean, they solved whatever issues prevented them from using that for MI300.

 

[BorisTheBlade82]

Here is another slide from the same presentation that even only shows the square in between the GMI links to be the BPV for the interconnect.

 

[TESKATLIPOKA]

View attachment 93147

Yes.

I really don't know why you still continue with your narrative how Strix Point will be BW starved.
We already have fast enough LPDDR5X on the market. Even handhelds already use 7500mbps for Zen4.
AMD is not so stupid to put 16CU IGP inside but not be able to feed It, that just doesn't make sense.

 

[FlameTail]

I really don't know why you still continue with your narrative how Strix Point will be BW starved.
We already have fast enough LPDDR5X on the market. Even handhelds already use 7500mbps for Zen4.
AMD is not so stupid to put 16CU IGP inside but not be able to feed It, that just doesn't make sense.

7500 not enough.

We need 8500.

 

[Glo.]

AMD is not so stupid

You sure?

 

[Philste]

I really don't know why you still continue with your narrative how Strix Point will be BW starved.
We already have fast enough LPDDR5X on the market. Even handhelds already use 7500mbps for Zen4.
AMD is not so stupid to put 16CU IGP inside but not be able to feed It, that just doesn't make sense.

Because AMDs APUs are Bandwith starved for 2 Years now?! It started with Rembrandt and now Phoenix is worse. Pheonix iGPU is clocked over 15% higher than Rembrandts and uses RDNA3, meanwhile it's not even 10% faster with same RAM and barely 15% with faster RAM. Also OEMs will always cheap out on faster RAM, so don't expect that every device comes with LPDDR5x-8533. New Tests of Desktop Versions also show that 7200 brings nearly no difference compared to 5200 (only about 7%). All this leads to the conclusion that Strix will be Bandwith starved to the moon.

 

[Glo.]

Because AMDs APUs are Bandwith starved for 2 Years now?! It started with Rembrandt and now Phoenix is worse. Pheonix iGPU is clocked over 15% higher than Rembrandts and uses RDNA3, meanwhile it's not even 10% faster with same RAM and barely 15% with faster RAM. Also OEMs will always cheap out on faster RAM, so don't expect that every device comes with LPDDR5x-8533. New Tests of Desktop Versions also show that 7200 brings nearly no difference compared to 5200 (only about 7%). All this leads to the conclusion that Strix will be Bandwith starved to the moon.

Also, 760M is just 15% slower than 780M while having 33% less CUs, than 780M.

If this is not memory starvation - I do not know what is.

 

[igor_kavinski]

If this is not memory starvation - I do not know what is.

Why couldn't it be latency?

Could also be driver overhead. Remember, the driver has to share system RAM with the CPU's other running processes. By the time it receives its quantum slice, the data it has may already be stale, needing to pull more which incurs another latency penalty waiting on the higher latency of LPDDR5 chips. The iGPU really needs its own slice of dedicated cache (256MB if possible).