Discussion Zen 5 Speculation (EPYC Turin and Strix Point/Granite Ridge - Ryzen 9000)

[DisEnchantment]

Speculate at will

 

[CakeMonster]

Was the 3950X or 5950X as limited with 32 threads on DDR4 as Z5 would supposedly be with >32t? Is there a formula for where it gets into trouble?

I'm absolutely fine with 32t for a while TBH, unless there's some brand new AI case or revolutionary stuff coming up. If you asked me 1-2 years ago I'd be leaning more toward wanting more cores, but as I've alluded to already, better IPC does to some extent make up for no extra cores. The 6c/12t Z4 parts are doing surprisingly well (even though I wouldn't want one). I'd absolutely prefer a 16c/32t Z5 over one that has to utilize thread prioritization, which is a big advantage for AMD now (outside of the 7950X3D).

 

[HurleyBird]

OK, actually thinking through it I need to walk back my back of the napkin math a bit (only a bit), since I made one incorrect assumption.

With DDR5 8000 at 2000MHz FCLK the X3D CCD gets 64GB/s and the c core CCD gets 64GB/s. The X3D CCD is not very memory sensitive, so for most tasks it has more bandwidth than it knows what to do with. The c core CCD cannot use the leftover bandwidth from the X3D CCD though, so it's not as simple as 50% more bandwidth feeding 50% more cores.

So, assuming that Zen5c is about as memory sensitive as Zen4 is, 2000 FCLK would be roughly equivalent to running Zen 4 at DDR5 4000. Not crushing, and plenty of tasks wouldn't mind, but not great either and a good number would be constrained. To the extent Zen5c may be more memory sensitive than Zen4, things start to get a bit more ugly.

If you can push FCLK up to 2666MHz for a 1:3 ratio with DDR5 8000, then the c core CCD could use around 85.33 GB/s or that, of roughly equivalent to DDR5 5333, which sounds fine for the vast majority of tasks.

Something like 2333MHz FCLK 1:3 ratio with DDR5 7000 could be a more realistic middle ground. Now the Zen5c CCD is roughly equivalent to a 16-core Zen 4 running DDR5 4666.

It may or may not be possible, but it could help binning if only one IF link needed to be validated to run at 2333MHz+ and you could use different ratios for each CCD.

Running this theoretical processor below DDR5 6000 and 2000MHz FCLCK is not something I'd recommend.

But, even at 2000 MHz FCLK, I don't see that making this hypothetical SKU *bad*. Those 16 cores won't be at their best, but will still usually beat 8, will be more energy efficient, and by running at a lower frequency than the X3D CCD, won't be a scheduling mess. Game performance is better, and you have more total compute. The main downside is that for single threaded tasks which don't respond to V-cache, performance will be lower than a regular 8950X with two normal 8-core CCDs due to the V-cache frequency hit.

 

[adroc_thurston]

2 x DDR5 8000 == 128GB/s == 2 x 2000 MHz IF links.

Ehhh someone forgot about IMC efficiency limits, especially in geardown modes.

with a more mature node

N7 is 5 years old, it can't be 'more mature'.

they certainly could if they wanted to for a halo part (Eg. bin for something like 2666MHz FCLK, which would give the same 1:3 ratio for DDR5 8000 that AMD recommends with DDR5 6000 on Zen 4).

why.

 

[A///]

Sorry, that's a big load of BS. Zen4 runs decently as low as DDR5 5200, while Zen5 should fairly easily run at DDR5 8000 or higher. A X3D CCD is far less bandwidth (and latency) sensitive than a non-V-cache CCD, and Zen5X3D should be noticeably less memory sensitive than regular Zen4. Zen5c is probably somewhere close to Zen4 in performance, but I'd guess may be a bit more memory sensitive depending on various factors (Zen5 architectural/lower level cache changes/whether we're still doing 2x 16MB L3s (probably) vs. a single 16-core CCX that shares the full 32MB).

But the point is, in a hypothetical part that mixes a Zen5X3D CCD with a Zen5c CCD, you're increasing core count by 50% and bandwidth by about the same via more mature DDR5. The important CCD (the X3D one) should be quite a bit less bandwidth sensitive than regular Zen4, while the c cores may be slightly more sensitive. Back of the napkin everything basically evens out. But even if it doesn't quite even out in the real world, being a little bit bandwidth constrained in some tasks is hardly going to make the product suck, it would just be slightly less awesome (with the potential of becoming more awesome in the future with newer AGESAs and even faster memory).

I suggest you email Mike Clark and suggest he's a dipstick for mentioning the bandwidth issue in the first place.

 

[HurleyBird]

Ehhh someone forgot about IMC efficiency limits, especially in geardown modes.

No, it's not 100% efficient, but it can be utilized. 1:3 helps which is why I brought that up initially.

N7 is 5 years old, it can't be 'more mature'.

No, it uses N6, and iirc was one of the first to do so, at least in the PC space. You can expect derived nodes to be comparatively more mature when they launch, but not fully mature.

why.

Explained earlier, and also in the post above.

 

[A///]

(especially so for rendering tasks such as Cinebench).

Cinebench is a benchmarking tool. I think you're thinking of Maxon's Cinema 4D.

 

[Joe NYC]

It’s a publicly traded company, they don’t do those types of things. The multi thread performance of the vanilla 8950X will already be very good (especially so for rendering tasks such as Cinebench).

Nullifying a competitive advantage of a competitor is good for shareholders.

 

[SteinFG]

2 x DDR5 8000 == 128GB/s == 2 x 2000 MHz IF links.

Ryzen 9 only, and Read only, and theoretical only.
Ryzen 7 (1 IFOP) can write to memory at most 32GB/s unless I'm missing something.

Edit: i'm definitely missing something, in some reviews r7 7700x gets 60GB/s write speed in aida memory test. Can anyone explain why?

And Buildzoid says that the ram and ifop are completely decoupled in am5, there's no benefit to syncing them like on am4.

 

[A///]

Nullifying a competitive advantage of a competitor is good for shareholders.

the competitor in this case is too busy hammering their fingers to entertain themselves.

 

[Saylick]

Okay, just talked to the head of IT at my company... they are going to move forward with upgrades by early next year for our main office, but there's a chance we could delay the upgrade for the office I'm based out of.

Fingers crossed that Zen 5 EPYC is out by then.

 

[Markfw]

Okay, just talked to the head of IT at my company... they are going to move forward with upgrades by early next year for our main office, but there's a chance we could delay the upgrade for the office I'm based out of.

Fingers crossed that Zen 5 EPYC is out by then.

If socket compatible, Zen 4 is the best out there right now by quite a margin,.

 

[Saylick]

If socket compatible, Zen 4 is the best out there right now by quite a margin,.

I'm hoping the baseline will be Genoa, but we definitely won't do CPU upgrades down the road because we upgrade once every 5-6 years. Socket compatibility is irrelevant for us because we don't upgrade annually.

 

[A///]

company? I thought you worked for a government geological dept.

 

[Markfw]

I'm hoping the baseline will be Genoa, but we definitely won't do CPU upgrades down the road because we upgrade once every 5-6 years. Socket compatibility is irrelevant for us because we don't upgrade annually.

If Genoa and Turn have the same socket. You start with Genoa, then when Turin comes out, just change chips. The platform is all the same, and compatibility.

 

[Saylick]

If Genoa and Turn have the same socket. You start with Genoa, then when Turin comes out, just change chips. The platform is all the same, and compatibility.

Yeah, we're not doing that. We don't replace or change chips after the computers are bought.

company? I thought you worked for a government geological dept.

Nope, private sector. Pay is arguably better, benefits... ehhhh debatable, but the work is far more interesting.

 

[Markfw]

Yeah, we're not doing that. We don't replace or change chips after the computers are bought.

Nope, private sector. Pay is arguably better, benefits... ehhhh debatable, but the work is far more interesting.

You are not buying the entire farm in one batch are you ?? I was saying, order the Genoa systems, and then after Turin comes out start ordering the Turin CPUs in the same pieces of hardware.

 

[PJVol]

And Buildzoid says that the ram and ifop are completely decoupled in am5, there's no benefit to syncing them like on am4.

How so? Afaik clock-domain crossing latency has always been an issue (FIFO), and btw, all uncore clocks can be decoupled since Rome.

 

[igor_kavinski]

I was saying, order the Genoa systems, and then after Turin comes out start ordering the Turin CPUs in the same pieces of hardware.

Corporate IT people don't do that. And besides, Dell and HP use custom compartment type cooling solutions that would make upgrading the CPUs pretty challenging for someone who has never done something like that before. And I think they would lose warranty the moment they open up the chassis to do something other than memory or storage upgrades. I don't think Saylick's IT team will be open to Supermicro, Tyan or ASROCK servers.

 

[A///]

Corporate IT people don't do that. And besides, Dell and HP use custom compartment type cooling solutions that would make upgrading the CPUs pretty challenging for someone who has never done something like that before. And I think they would lose warranty the moment they open up the chassis to do something other than memory or storage upgrades. I don't think Saylick's IT team will be open to Supermicro, Tyan or ASROCK servers.

dell and hp make it so a child can change it easily.

 

[igor_kavinski]

dell and hp make it so a child can change it easily.

Maybe everything except the CPU cooler. That one looks like some non-standard monster you don't want to touch.

 

[A///]

Maybe everything except the CPU cooler. That one looks like some non-standard monster you don't want to touch.

I was referring to the cpu cooler. It's simple once you figure it out.

 

[Fabius]

AMD let slip that Raphael-X parts would come later, so a lot of people skipped over the 7950X. The 7950X3D predictably sold quite well.


Just look at how well Zen3 sold. You couldn't get anything but a 5800X for a long, long time. Unless you paid scalper prices. Zen4 did not offer a repeat.

I'll be impressed if AMD can pull that off again, especially at a higher price point. Somehow I don't think that'll happen though.

In client PCs, AMD has been at a standstill as a market share for a couple of years. Furthermore, in the last 4 consecutive quarterly it has recorded losses, I am always talking about client PCs.

 

[uzzi38]

In client PCs, AMD has been at a standstill as a market share for a couple of years. Furthermore, in the last 4 consecutive quarterly it has recorded losses, I am always talking about client PCs.

Yeah, because as they've been consistently saying on their earnings calls, they're undershipping. They don't want to sell to the client markets while they're as down in the dumps as they are.

 

[eek2121]

AMD's next-gen Ryzen 8000 APU spotted with 16 RDNA3.5 GPU cores - VideoCardz.com

AMD Ryzen 8000 12-core Zen5 “Strix Point” APU spotted with 16 RDNA3.5 Compute Units At long last, we have a leak that confirms the configuration of AMD’s upcoming APU. It shouldn’t come as a surprise to any readers by now that the Ryzen 8050 APU series will debut with 12 cores. There have been...

videocardz.com

Interesting, if legit.

 

[TESKATLIPOKA]

AMD's next-gen Ryzen 8000 APU spotted with 16 RDNA3.5 GPU cores - VideoCardz.com

AMD Ryzen 8000 12-core Zen5 “Strix Point” APU spotted with 16 RDNA3.5 Compute Units At long last, we have a leak that confirms the configuration of AMD’s upcoming APU. It shouldn’t come as a surprise to any readers by now that the Ryzen 8050 APU series will debut with 12 cores. There have been...

videocardz.com

Interesting, if legit.

For those who are lazy to open It. Of course once more many mistakes are there.