Who will be next Intel CEO?

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Spartak

Senior member
Jul 4, 2015
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Yeah 10 nm at this point might be unfixable.

Delaying till 2019 buys them another year to fix the issue but like you I'm skeptical. Maybe EUV will be mature enough to circumvent some critical quad patterning and they can adjust the process without too much additional costs. But at some point you need to cut your losses and just move forward.

edit: come to think I read somewhere ASML is pretty booked on EUV and Intel was on the conservative side with ordering. Seems they took a huge risk without a backup plan for 10nm.
 
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ksec

Senior member
Mar 5, 2010
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That's not what I wrote? Notice the rather essential [develop Pentium M] into Core. Yes Pentium M was developed during Barrett, Banias probably too. But it was Otellini that made the switch from Pentium 4 to the Core Microarchitecture not just for mobile but for their entire lineup, including new branding. That takes guts and vision.
It's even likely that the development of Core started at the end of Barrett's tenure, but seeing how Otellini from the start put his full weight behind it and swayed Apple, I would not surprised if, as president (and COO) he was one of Cores main internal proponents.


Again you read something I didnt write. The rumor isn't nonsense, its there.
It might even be true that they are debating that internally. Is it likely they will actually skip? Probably not. But that's a different claim altogether from what I wrote.
And according to people far more knowledgeable than me there are indeed fundamental problems with their 10nm approach, so saying '10nm is good' kindof betrays you don't know what you're talking about. The 'too aggressive' specifically refers to the quad multipatterning in combination with the use of cobalt.

Try reading a bit more careful next time, I don't think we disagree on any point fundamentally.

Um... Sigh.

Otellini vision? turning into Core 2 ?...... I think now I understand why Pat Gelsinger left, and he is not coming back.

Ashraf Eassa? The rumor isn't nonsense? Ashraf Eassa has been dead wrong on everything about Intel - Apple, And dead wrong on all previous of his " explanation" of how great 10nm will be prior to him turning to against Intel.

You are right. I don't know what I am talking about. And neither do anyone of us here. Nor do the Intel engineers know when it will actually yield. 10nm Is good because it is the best out there. But It doesn't yield. And that is a fact. Of coz there is going to be problem with SAQP. Just like 14nm. Triple Patterning which arguably TSMC isn't even on the same level. This is speaking as an TSMC proponent who multiple Intel hard core fans on Aanadtech, also incidentally decided to disappear once 10nm didn't actually yield and has been cheering all along saying my TSMC figures were utter crap. Oh, and my name with TSMC is on someone's signatures.

Intel decide to optimise from a cost perspective / transistor density. Absolutely nothing wrong with it. The problem is they are not executing on time. The only thing they "might" skip 10nm for either High Performance or Low Energy node. Depending how far along 10nm is in both regards. But Intel 7nm is so reliant on EUV, which is even more difficult to get right, as if 10nm is not aggressive enough.
 
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Spartak

Senior member
Jul 4, 2015
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It seems you lack basic knowledge of english? Try to understand what I wrote instead of sighing, it makes you look daft.

The rest of your reply reads as a confused fanboy rambling.




Insulting members and calling anyone a fanboy is not allowed.


esquared
Anandtech Forum Director
 
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ksec

Senior member
Mar 5, 2010
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It seems you lack basic knowledge of english? Try to understand what I wrote instead of sighing, it makes you look daft.

The rest of your reply reads as a confused fanboy rambling.

You implied it was Otellini "vision" that got where Intel to Core 2. And I utterly disagree. Because it doesn't take "guts and vision. He simply had no choice. That is like saying BK has the guts and vision to make 96% Server Market share for Intel during his era. Otellini is the first and only Intel CEO who doesn't have an Engineering background. He does have an MBA, so every move he has made, are based on predictable financial outcome. And the reason why he pass up the opportunity for iPhone SoC. Pat wrote an internal paper detailing how Intel were down the wrong path, and hence changed course of Intel ever since. And as he was the CTO during previous era that dictate those roadmap.

I said the "rumours" was compete nonsense. Nothing directly at "you". While you wrote

Again you read something I didnt write.

And even if the rumours were from the two people, doesn't make the rumour creditable. And I have pointed out they have been wrong in the past again.

You then

And according to people far more knowledgeable than me there are indeed fundamental problems with their 10nm approach, so saying '10nm is good' kindof betrays you don't know what you're talking about. The 'too aggressive' specifically refers to the quad multipatterning in combination with the use of cobalt.

Then explain to me how 10nm isn't technically good? Given what has been shown on paper in IEDM. If you define "good" include yield then I let you have it. but I did wrote and I quote

10nm is good, just yield is crap.

And the use of Cobalt likely has nothing to do with their yield. It is not like they are the first to use it, GF also uses cobalt in 7nm, just not used as much as Intel, and has higher metal pitch to compensate for it. SAQP is an industry first, no other players are attempting Quad Patterning without EUV.

So point to me how TSMC, GF or even now the delayed Samsung 7nm, how Intel 10nm is not "good".

Oh, I wrote in 2016 how TSMC is going to overtake Intel. And it is left in Witeken signature,

https://forums.anandtech.com/members/witeken.339902/

Talk about me being an Intel Fanboy? Yeah. May be I am daft.

And before you reply, none of the replies had any direction or word of rude or insult to you. But the same couldn't be said to you.

I can see why now Arachnotronic don't come up to Anandtech as often.
 
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IntelUser2000

Elite Member
Oct 14, 2003
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Barrett and Otellini were mediocre. The former was just in the right place when the PC market was getting bigger. They were not bad CEOs, but not excellent. Just a typical one.

Otellini fired Pat and he missed the mobile boat, the problems which are still being felt.

Kraznich was idiotic and psychotic. If Otellini pointed the company towards a disaster, Kraznich then went full speed to it.

I hope the next is much better but the trends are not looking good. It's not like this time Intel can "Conroe" it either. Sure, maybe they'll do better than AMD, but the real competence is now at Apple.
 
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maddie

Diamond Member
Jul 18, 2010
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.............................................................................................................................................................................................
Utter nonsense. 10nm is good, just yield is crap. Even if they ironed it out next year it is still competitive. Just not a generation lead they are used to, and the investment gone into 10nm is far too high to skip.
...............................................................................................................................................................................................
Lisa Su took worked under immense pressure, perfect execution to get to AMD where it is at today, that is 4 years. And they don't have to worry about the manufacturing side, which the GF has been in good hands also for those 4 years. But Intel do have a few uArch in the pipeline, and they can do price war.
..................................................................................................................................................................................................
1st part, and I quote.
"Utter nonsense. 10nm is good, just yield is crap."

How exactly does that work?

2nd part, and again I quote
"But Intel do have a few uArch in the pipeline, and they can do price war."

I keep hearing this little voice repeating, "margins and share price".
 

aigomorla

CPU, Cases&Cooling Mod PC Gaming Mod Elite Member
Super Moderator
Sep 28, 2005
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Xi Jinping will obviously be the next CEO of intel after China buys them out completely. :p
 

NostaSeronx

Diamond Member
Sep 18, 2011
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Update to this: https://www.bizjournals.com/sanjose/news/2018/09/05/intel-ceo-candidates-shortlist-intc.html
/Bloomberg's List by Ian King

1. Sanjay Jha
2. Anand Chandrasekher
3. Navin Shenoy
4. Murthy Renduchintala
5. Renée James

Sanjay Jha appeared in other lists as well.
https://www.oregonlive.com/silicon-forest/index.ssf/2018/06/intels_ceo_search_heres_what_c.html
By Mike Rogoway

https://www.fool.com/investing/2018/07/01/my-short-list-for-intels-next-ceo.aspx
By Ashraf Eassa

So, Sanjay Jha if not for Mubadala going for Dresden(1.75 billion USD) and Chengdu(>9 billion USD). Would have probably made GlobalFoundries a FinFET powerhouse. If lets say Malta got that 10 billion USD instead. Of the outsiders, he has the least baggage.

Not being money tight, Sanjay Jha probably could help Intel's FDSOI products from 14nm to 7nm. Giving Intel differentiated products for Intel custom foundry, while not sacrificing FinFET and beyond.
 
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NostaSeronx

Diamond Member
Sep 18, 2011
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Wait, so now Intel will start doing FD-SOI? :p
They have had FDSOI for sometime. They didn't go to it because it was difficult for them to deplete the channel.
And CMT. Don't forget CMT.
That is part of VISC architecture.

===
If Sanjay Jha is the person getting the CEO seat. Then, Intel's "UTB-SOI" from "TeraHertz/DST-Planar/DST-Single" generally would be ramped up.

He was also the Chairman of SoftMachines.

1. Increase profits from Intel Custom Foundry.
a. Add differentiated options.
b. Accelerate FinFET and beyond.
2. Lead Intel into IA-VISC.
3. Probably can do whatever everyone else can on the list.

---
CMT & VISC comment:
http://www.chip-architect.com/news/2001_10_02_Hammer_microarchitecture.html
- Hans de Vries

https://patentimages.storage.googleapis.com/pages/US6119223-2.png
https://patents.google.com/patent/US6119223A/en
https://patents.google.com/patent/US6266763B1/en
- Patent in question, owned by GlobalFoundries.
https://www.wsj.com/articles/SB939078537722111678
"Compounding the company's problems, AMD's chief architect of the SledgeHammer chip, James Keller, resigned about a month ago. A company spokesman said Mr. Keller's departure won't affect the chip's schedule, but Mr. Gwennap called it a red flag."
James Keller = Jim Keller

https://i.imgur.com/3uhwtk2.png
- VISC Concept
 
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Edrick

Golden Member
Feb 18, 2010
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Otellini was one of Intel's most succesful CEO's. His eight year tenure saw intel move away from the Pentium4, develop the Pentium M into Core 2, Nehalem, Ivy Bridge, Sandy bridge, Haswell and probably into the development of Skylake.

Yea, and he almost killed AMD in the process and killed competition in the market which drove consumer prices higher. Good for Intel, bad for the rest of us.

Brian Krzanich was probably the worst CEO Intel ever had. In his five year tenure he brought the Core architecture from Skylake to...well still Skylake. The disappointing IPC improvement of Skylake and lack of any architecture improvements after, paints a picture of a CEO that all but halted R&D developement the day he took office.
This five year standstill has brought AMD and even Apple/ARM into striking distance of Skylake.

And at the same time gave us the competitive marketplace we have today with real choices. Bad for Intel, great for the rest of us.

So I suppose the best and worst CEO's at Intel are subject to your point of view. :)
 
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Hitman928

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Apr 15, 2012
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They have had FDSOI for sometime. They didn't go to it because it was difficult for them to deplete the channel.

*cough*What a load of BS*cough*


Why are you linking to something written about the original Hammer (K8) architecture back in 2001, a decade before Bulldozer came out? Hammer wasn't a CMT architecture and I didn't see any mention of CMT or VISC in that link.
 
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CHADBOGA

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Mar 31, 2009
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Why are you linking to something written about the original Hammer (K8) architecture back in 2001, a decade before Bulldozer came out? Hammer wasn't a CMT architecture and I didn't see any mention of CMT or VISC in that link.

Because he is NostaSeronx.
 
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NostaSeronx

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*cough*What a load of BS*cough*
https://ieeexplore.ieee.org/document/979585/
and "High performance fully-depleted tri-gate CMOS transistors"
Fully-depleted (FD) tri-gate CMOS transistors with 60 nm physical gate lengths on SOI substrates have been fabricated. These devices consist of a top and two side gates on an insulating layer. The transistors show near-ideal subthreshold gradient and excellent DIBL behavior, and have drive current characteristics greater than any non-planar devices reported so far, for correctly-targeted threshold voltages. The tri-gate devices also demonstrate full depletion at silicon body dimensions approximately 1.5 - 2 times greater than either single gate SOI or non-planar double-gate SOI for similar gate lengths, indicating that these devices are easier to fabricate using the conventional fabrication tools
It was to hard says Intel. With Samsung, STM, GlobalFoundries saying otherwise.


In "A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-K Metal-Gate CMOS Technology"
"The design contains fully integrated dynamic forward-body-bias to achieve lower voltage operation while keeping low the area and power overhead. The dynamic sleep design, which was developed at the 65nm node (Zhang et al., 2005), is further enhanced with op-amp-based active-feedback control and on-die programmable reference-voltage generator. The new sleep design reduces the effect of PVT variation, leading to further power reduction. The modular architecture of the design also enables the 16KB-subarray to be used directly as the building block for a 6MB L2 cache in the Core^TM 2 CPU (George, 2007). The design operates over 3.5GHz at 1.1V."
The return of body biasing will re-utilize older engineers for new designs.

scis.scichina.com/en/2016/061402.pdf
"Contrary to the common belief that FDSOI technology only holds promise in niche low-power applications, the results of the above ASIC chip demonstrate its benefit for mid- and high-performance applications. Any application that is concerned about active power, whether an always-on IoT/wearable or a high performance server/networking chip, should consider the implications of FBB and low voltage operation offered by FDSOI."

Unlike, Samsung and GlobalFoundries. Intel's UTB can be done with Shin-Etsu Handotai. Which is super aggressive and flaunting their UTB ready muscles.

2011 and then onward marked a shift in Intel. 2.5D/3D ICs allow UTB and Tri-gate to be used together for the best advantages of each.
Why are you linking to something written about the original Hammer (K8) architecture back in 2001, a decade before Bulldozer came out? Hammer wasn't a CMT architecture and I didn't see any mention of CMT or VISC in that link.
SoftMachines based their designs off that. So, Intel has;
1. Jim Keller who built or touched upon the foundation of the VISC architecture, the CPU core.
2. SoftMachines group who built VISC and had path finding to Ordos.
As of currently: TigerLake is Ordos(WLC) and AlderLake is Ordos+(OCC).


Sanjay Jha was also considered the first time before BK, and he is in the short-list a second time.
The roadmaps built by Michael Mayberry also indicate that Intel for 2.5D/3D must also open up.
- Quantum Well and UTB-SOI
- FinFETs, GAA: Nanowire/Nanosheet, and Dots/Vertical.

For example,
- stacked SRAM with UTB-SOI means low variation, low area, lower overhead, lower voltage.
- Successor to "Tangle Lake" , cheaper Qubits, etc.
- Intel's Lolhi which has a die size of 60 mm squared. Would probably be better on UTBB SOI, etc.

Sanjay Jha getting the position would put some credence to Intel-GlobalFoundries "stuff". IBM would probably fling their support in on Sanjay Jha if they get SOI FinFET/Nanosheet. Even, if they consider it a deal with their competitor.

There is something against Sanjay Jha however:
http://roshmere.com/
^He is the CEO of this.

http://www.computerworld.in/news/intels-alexis-bjorlin-explains-why-silicon-photonics-matter
https://www.ofcconference.org/en-us...re-demonstrates-800gbps-per-wavelength-all-s/
imho, that is more likely to be purchased than Ampere with Renee James.

http://ieeetv.ieee.org/technology/i...-not-wait-for-the-killer-app?rf=channels|104&
https://ieeetv.ieee.org/conference-...world-forum-santa-clara-2018?rf=channels|104&
Data-centric Intel anyone?
While not sacrificing the Foundry?
 
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NostaSeronx

Diamond Member
Sep 18, 2011
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I don't know if it's a language barrier or what, but your link there does not support your argument. . . at all.
Pfft.

What is a box? "Insulator"
21terahertz.gif

https://i2.wp.com/www.pctechguide.com/wp-content/uploads/2011/09/21terahertz.gif?resize=430,176

terahertz-trigate-transistor-9-638.jpg

https://image.slidesharecdn.com/ter...tz-trigate-transistor-9-638.jpg?cb=1393547888

YsMiDls.png

https://i.imgur.com/YsMiDls.png

The only language barrier is there is none. What is a Si on a buried oxide? A SOI transistor.

Do you have a language barrier?
1. Intel has FDSOI.
2. Intel post-2011 planned for three FDSOI nodes on: 14nm, 10nm, 7nm.
3. FDSOI doesn't have the issues it had anymore.
4. etc.

Who better to lead the implementation of FDSOI at Intel, than Sanjay Jha?
 

UsandThem

Elite Member
May 4, 2000
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Keep the debate civil.

This thread is who the next Intel CEO will be.
For technical discussion on CPU tech (or discussing things like FD-SOI),
post in the appropriate thread.

AT Mod Usandthem
 
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DrMrLordX

Lifer
Apr 27, 2000
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Hey maybe Neutron Jack is available. He's only 82.

Or hmm, hell just give Raja the job. That would be pretty funny.

Orrrr they could try to poach Hector Ruiz from Advanced Nanotechnology Solutions. Yeah that's the ticket!

Murthy? As if.
 
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jpiniero

Lifer
Oct 1, 2010
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Still don't expect Intel to announce a new CEO for awhile. At the very least, they will wait until after they give some sort of guidance on 2019 earnings/admit they are going to lose a ton of revenue because of Rome.
 

DrMrLordX

Lifer
Apr 27, 2000
23,180
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Why accept the CEO position before 10nm is starting to ship?

Whoever is taking the reins at Intel has the chance to dig them out of the gaping pit into which they have fallen. Sure, the earnings aren't there yet, but all the future indicators are pretty bad. The time for the turnaround is now.
 

cbn

Lifer
Mar 27, 2009
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Whoever is taking the reins at Intel has the chance to dig them out of the gaping pit into which they have fallen.

(snip)

The time for the turnaround is now.

Optane is the future.

IA + Optane, AMD + Optane, ARM + Optane, Power + Optane, SPARC + Optane, MIPS + Optane, RISC-V + Optane, GPU + Optane, etc.

....so probably someone who understands that well (or at least well enough).
 
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