I'm assuming two things:
1) AMD won't tear up the CCX to make a 6 core one for Zen 2.
2) It appears that the iGPU on the current Raven Ridge processor is hitting the limits of what can efficiently be done with dual channel DDR4.
Assuming the scaling for 7nm would make the current RR die about 30% the size that it currently has, I'll guess the following:
1)The next APU die will have 2 X 4 core CCX units with more L3 cache than the current ones. Probably will go back to the 8MB per core like PR. This should take some memory load off of the DRAM controller, providing more for the iGPU.
2)The iGPU will see minimal tweaking, maybe one or two more CUs to take advantage of the marginal increase in available memory bandwidth.
3)In the same package size, with the above changes, there is room for a non-trivial L4 cache. That could be implemented to improve iGPU performance. I doubt that we'll see that though. There is also the possibility that, instead of doing an L4 cache, they implement a HBM controller instead. This can allow AMD to use a smaller die, and implement a back channel HBM stack in the same package using MCM or something like EMIB for high end APUs while leaving it off for low end products. This would be in keeping with AMD's current philosophy and offer substantial performance improvements for their APU stack.
The total die size will be reduced, increasing die yield per wafer, which helps AMD for production efficiency. This will be a compelling product for mainstream business and home OEM desktops and traditional format laptops.
Assuming that AMD revenues continue to increase as they have, and that they have more engineering resources, I expect that we'll also see a smaller APU die eventually created that is essentially a 7nm shrink of an optimized Raven Ridge die with the Zen2 core and uncore improvements. This can be targeted at the lower power ultraportable/convertible market.