What happens to nvidia?

[Caribbean Geek]

Fermi had been using double vias from the beginning.

Do you have a link to proof it?

 

[Kenmitch]

Dual chip is plagued with problems since the beginning. Lots of games don't like CF and SLi. Having a seperate GPU for cuda and physX is a good idea, but it really isn't like ATI is going to play handicap. ATI had been all out against Nvidia in terms of the quality of the chip and Nvidia really don't have the room to play fancy.

I wasn't thinking dual chip as in CF or SLI but was thinking more like dual chip as in 1 chip handles the gpu part and another handle's all the xtra stuff. The driver would take care of the details. The driver would see the second chip kinda like a dedicated physX card. Seems like this wouldn't be too complicated to implement. To me it seems like it would open up more options and markets for nvidia.....Kinda like ageia did with physX a dedicated card for the purpose. But in this case just a chip that could be put into and added to multiple devices such as video cards, set top box's, etc.

 

[Seero]

I wasn't thinking dual chip as in CF or SLI but was thinking more like dual chip as in 1 chip handles the gpu part and another handle's all the xtra stuff. The driver would take care of the details. The driver would see the second chip kinda like a dedicated physX card. Seems like this wouldn't be too complicated to implement. To me it seems like it would open up more options and markets for nvidia.....Kinda like ageia did with physX a dedicated card for the purpose. But in this case just a chip that could be put into and added to multiple devices such as video cards, set top box's, etc.

Think of it this way. ATI cards have a tessellation unit on them and does tessellation really well, but what about the times when there tessellation is not needed? It then become an idle unit. Plus, it isn't scalable.

CUDA cores on the other hand does physX when needed, and does tessellation too, when needed. When those are not needed, it simply max out FPS. This is the meaning of GPGPU where it does was never programmers throw at them. The Fermi design greatly reduced the idle time between instructions, maximizing the utility of GPU. The advantage of Fermi over GT200 is the minimum FPS, not the maximum.

It is a tradeoff. You can have a unit that does everything half good, or units that does specific tasks that are idle most of the time. It is Nvidia's decision to go with the former, and I am eager to see the result. With the CUDA design, they can make a server(computer) that consist of only GPUs, and no units are idle during load.

We can't see the differences between having a physx unit or not, but we can see the difference between having a tessellation unit or not. You be the judge on that.

 

[Scali]

Do you have a link to proof it?

Already linked to the thread earlier. Keysplayr got the info directly from nVidia.

 

[Caribbean Geek]

Already linked to the thread earlier. Keysplayr got the info directly from nVidia.

OH I see, then I wonder why they had so many low yields, probably are related to the big die size, I knew that the GT220/240 weren't in vain after all.

 

[busydude]

OH I see, then I wonder why they had so many low yields, probably are related to the big die size, I knew that the GT220/240 weren't in vain after all.

Low yield thing was Charlie's FUD.

 

[Caribbean Geek]

Low yield thing was Charlie's FUD.

Charlie has some FUD power around, that would explain why I've never saw issues of availability with the GTX 480 when launched, but they didn't sold out either, there's healthy amounts of such cards in Newegg. I think that the GTX 460 1GB is the only card that nVidia is selling well enough for now, the GTX 465 is like the HD 5830, higher power consumption and slower than their bigger brothers, both should be shot and buried at the bottom of the sea

 

[Seero]

Charlie has some FUD power around, that would explain why I've never saw issues of availability with the GTX 480 when launched, but they didn't sold out either, there's healthy amounts of such cards in Newegg. I think that the GTX 460 1GB is the only card that nVidia is selling well enough for now, the GTX 465 is like the HD 5830, higher power consumption and slower than their bigger brothers, both should be shot and buried at the bottom of the sea

Don't give out ideas to pollute the sea.

Damn, got combo attacked by answering...

 

[Daedalus685]

Low yield thing was Charlie's FUD.

Implying that there are no yield problems or that they are not a bad as reported?

 

[railven]

Already linked to the thread earlier. Keysplayr got the info directly from nVidia.

You should point out that Keys also said they were using single vias too. There was no clear distinction of which products got single and which got doubles.

 

[Scali]

You should point out that Keys also said they were using single vias too. There was no clear distinction of which products got single and which got doubles.

They said that all Fermi-based products (both GF100 and GF104) have always used double vias.

And yes, the thread also discusses the obvious fact that you never use double vias exclusively. You'll use single vias in areas where possible.
That's nothing new, both nVidia and AMD do that (as well as every other major chip designer).

Can we now please drop this non-subject? TSMC has offered double via technology since their 130 nm process (or perhaps even sooner, can't recall). Why is everyone talking as if it is a new thing for 40 nm, and nVidia would somehow not know about it?
Heck, look at this document from 2003(!) from TSMC, discussing it on page 4:
http://www.tsmc.com/download/english/a05_literature/September_2003.pdf

 

[railven]

They said that all Fermi-based products (both GF100 and GF104) have always used double vias.

And yes, the thread also discusses the obvious fact that you never use double vias exclusively. You'll use single vias in areas where possible.
That's nothing new, both nVidia and AMD do that (as well as every other major chip designer).

Can we now please drop this non-subject? TSMC has offered double via technology since their 130 nm process (or perhaps even sooner, can't recall). Why is everyone talking as if it is a new thing for 40 nm, and nVidia would somehow not know about it?
Heck, look at this document from 2003(!) from TSMC, discussing it on page 4:
http://www.tsmc.com/download/english/a05_literature/September_2003.pdf

Woah dude, chill out. I'm just saying if you are going to use Keys as the reference include everything he said:

Heard back from NV. They utilize a mixture of single and double vias in all Fermi GPU's.

Anticipating the next questions: "Well, which parts are single and which parts are double?"

If you guys need to know this, (and I do not have this answer) it's time to put down the keyboard and go play baseball. Even if it's on a console.

And the only reason I clearly remember this is because the way you reacted in the thread to Keys saying [paraphrase] "you're both right."

Relax.

 

[Daedalus685]

As far as I know IDC is the only one with engineering experience on ICs on these forums...

To break down what they did or didn't do to three factors in something will a billion parts is ridiculous. I have a hard time believing that the media reports on how the GPUs are put together (something I don't fully understand) are any more accurate to reality than those reporting how laser physics (something I do understand) will change the world. i.e. highly complicated things are almost always reported misleadingly or flat or incorrectly. Fun question... put up your hand if you actually know what a via is for, why you would need two instead of one, and what difference it makes other than "two is better than one". ATI likely learned some tricks with the 4770 that they did not know before.. perhaps one of them was exactly where to use double vias... Nvidia likely learned the same things. Given that the 4770 was within a few months of the 240ish cards we can likely assume both learned about the same things at about the same time, and if anyone learned more than another it is as far above our heads as the moon.

So for us to argue about it is really akin to arguing how well that tractor beam posted in OT will work...

If we know how much it costs to make each GPU, how much they sell for, and how much the R&D cost we can make educated guesses on who is better off (who will make or lose money and for how long... of course we don't know any of these numbers but from wildly differing rumours). We can comment on which card is the best product. We can even guess on which company will explode... But we really have no basis for talking about which GPU was built using the soundest engineering.

I only mention this because it all of a sudden came to me the other day that "Gee, the couple people who actually are experts on GPUs and ICs probably find the talk on it just as enlightening as I find some physics reports... I've become what I hate!"

Deep breath everyone, that is all.

 

[Scali]

I don't need to include everything he said, as it is not relevant.
The FUD was that nVidia did NOT use double vias, while they did.
Obviously every chip design will use single vias wherever possible.

And I don't need to 'chill out' or 'relax', as I'm perfectly calm.
Just getting tired of people who keep up bringing this FUD.
As you see, double vias are neither new nor some kind of secret technology. Thinking that nVidia somehow wouldn't have any experience with designing circuits with double vias is just very naive. It is also grossly underestimating and even insulting nVidia's engineering team.

 

[railven]

I don't need to include everything he said, as it is not relevant.
The FUD was that nVidia did NOT use double vias, while they did.
Obviously every chip design will use single vias wherever possible.

And I don't need to 'chill out' or 'relax', as I'm perfectly calm.
Just getting tired of people who keep up bringing this FUD.
As you see, double vias are neither new nor some kind of secret technology. Thinking that nVidia somehow wouldn't have any experience with designing circuits with double vias is just very naive.

Okay guy. Should go back to the other thread. All I'm saying is, even Keys himself didn't say it was FUD the [paraphrase] "you're both right" comment.

But, hey, I'm just going by what was said. You're reaction here is the same as it was then. Sooo...I'm just ducking out now before it gets worse.

Cheerio!

 

[Daedalus685]

I don't need to include everything he said, as it is not relevant.
The FUD was that nVidia did NOT use double vias, while they did.
Obviously every chip design will use single vias wherever possible.

And I don't need to 'chill out' or 'relax', as I'm perfectly calm.
Just getting tired of people who keep up bringing this FUD.
As you see, double vias are neither new nor some kind of secret technology. Thinking that nVidia somehow wouldn't have any experience with designing circuits with double vias is just very naive. It is also grossly underestimating and even insulting nVidia's engineering team.

So what exactly does "double via" mean anyway??

Those I am familiar with are simply conductive vertical connections between layers. Is this the same meaning in an IC as well? Are we really arguing over how many connectors each trasistor uses? Does double really even mean "two" or does it mean twice as volumous? Granted failure of a connection would kill the IC but this is probably one of a thousand things they "double up on" to ensure a working chip in the end. Perhaps vias are something totally different in a complicated IC...

 

[busydude]

Nope, AMD has never released a single driver for FreeBSD... and the open source support for most GPUs (especially newer ones) is horrible.
nVidia has supported FreeBSD x86 for a few years now, and a few months ago, they also started releasing x64 drivers. So I'm pretty happy about that (I've been running the x64 version for quite a while now).
nVidia also supports Solaris btw.

All these OSes use the same Xorg stuff, and mainly require OpenGL/OpenCL support. So once you have a working linux driver, it should not be THAT difficult to also add support for FreeBSD and Solaris to your codebase. But nVidia is the only one who has made the effort.
For all other GPUs, you're completely dependent on the bundled open source drivers in Xorg.

Thanks for answering.

All these things add up perfectly, Nvidia has developed a complete ecosystem surrounding their cards.

No wonder AMD has no significant presence in professional space.

 

[Scali]

So what exactly does "double via" mean anyway??

Those I am familiar with are simply conductive vertical connections between layers. Is this the same meaning in an IC as well? Are we really arguing over how many connectors each trasistor uses? Does double really even mean "two" or does it mean twice as volumous? Granted failure of a connection would kill the IC but this is probably one of a thousand things they "double up on" to ensure a working chip in the end. Perhaps vias are something totally different in a complicated IC...

Yea, that's pretty much it.
Double via means two vias connecting to a single transistor.
There are also triple vias, quadruple, etc.
And then there are also variations, such as the 'fat' vias that TSMC describes in the document I linked earlier, which you could describe as 'more volumous'.

 

[Scali]

Okay guy. Should go back to the other thread. All I'm saying is, even Keys himself didn't say it was FUD the [paraphrase] "you're both right" comment.

But, hey, I'm just going by what was said. You're reaction here is the same as it was then. Sooo...I'm just ducking out now before it gets worse.

Cheerio!

Why do you bring it up again in the first place? Did you just admit to trolling?

 

[Daedalus685]

Yea, that's pretty much it.
Double via means two vias connecting to a single transistor.
There are also triple vias, quadruple, etc.
And then there are also variations, such as the 'fat' vias that TSMC describes in the document I linked earlier, which you could describe as 'more volumous'.

That is what I thought... When the topic first came up I assumed the acronym via was used for something else in ICs as to argue about how a company would choose to use more connectors when they had troubles (and knew they would on a new process) with them being broken was brilliant baffled me..

I can complain about a lot of things involving Nvidia... and do... but this really seems like the same sort of BS that is over hyped and incorrectly represented in many media reports on science + engineering + etc...


To be clear... While I don't agree with many of scali's positions I must agree that to use doubling of vias (as tried and true as using a larger gauge of wire when required) as an example of how epic a certian engineer may be is rediculous. It is likely the simplest thing they could have done to improve yields and is likely at the bottom of a list of dozens of things to help boost up yields of such a large GPU that were tried and are all far more complicated. IF there is any truth to ATI learning more about 40nm its place is in a doctoral paper.. not a tech forum.

 

[Caribbean Geek]

Originally posted by Scali:
Can we now please drop this non-subject? TSMC has offered double via technology since their 130 nm process (or perhaps even sooner, can't recall). Why is everyone talking as if it is a new thing for 40 nm, and nVidia would somehow not know about it?

I don't need to include everything he said, as it is not relevant.
The FUD was that nVidia did NOT use double vias, while they did.

And I don't need to 'chill out' or 'relax', as I'm perfectly calm.
Just getting tired of people who keep up bringing this FUD.

As you see, double vias are neither new nor some kind of secret technology. Thinking that nVidia somehow wouldn't have any experience with designing circuits with double vias is just very naive. It is also grossly underestimating and even insulting nVidia's engineering team.

Why do you bring it up again in the first place? Did you just admit to trolling?

I think that railven is refering to your posts that seems a bit on the rude side. :|

 

[Scali]

I think that railven is refering to your posts that seems a bit on the rude side. :|

I thought he was on the rude side himself... trolling and telling someone to "chill out", "relax", and other things.
Was actually doubting whether I should report him.
You've made up my mind for me now.

 

[Idontcare]

As for increasing yield with larger dies do you have anything substantive to add? Because simple math says you are wrong.

I'm still reading down the thread, but perchance this question hasn't been addressed to satisfaction the answer is that it is a trade-off between parametric yield and functional yield.

http://forums.anandtech.com/showpost.php?p=27924059&postcount=13

Once factor determining parametric yield is what designers refer to as "margin"...to increase the electrical noise margin in a chip you might want to boost the signal which means higher drive-current at a given Vcc which means wider transistors which means lower xtor density.

The trade-off in improving parametric yields against margin issues is that of functional yield loss, which is primarily die-area dominated and drive entirely by defect density of the fab.

As fabs mature, functional yields become less of a probe yield impacter (see my thread link) and parametric yield becomes the dominate probe yield limiter.

Nvidia knows how to design large dies for manufacturing, GT200 was an eye-opener for just about anyone in the industry who deals with large die production issues.

 

[Idontcare]

Yea, that's pretty much it.
Double via means two vias connecting to a single transistor.
There are also triple vias, quadruple, etc.
And then there are also variations, such as the 'fat' vias that TSMC describes in the document I linked earlier, which you could describe as 'more volumous'.

There are two dimensions at play here.

First is the fact that for a given process node the design rules basically set limits on the range of possible metal widths and pitches, we in the layman world tend to get led down the path of focusing on just the minimum pitch limits.

For example the minimum diameter allowed for a via in TSMC's 40nm will be different depending on the specific metal level. But you can always have a larger via diameter than the design rule minimum.

So a M2 (metal 2) via might have a min diameter of 70nm but you could build an IC that uses 400nm diameter via's if you liked. (with the trade-off being the metal pitch increases, and so too the die-size)

Go up to M5 (metal 5) and the minimum via diameter might be 90nm or 120nm, but you could also implement 400nm diameter vias here as well if you liked.

The second dimension is what TSMC calls "fat" vias. "Fat" vias are actually referred to as "rectangular" vias in the industry. Remember the documents you get to see in the public domain have been dramatically dumbed down, in both its vernacular as well as its technical depth, as they tend to be used for marketing crutches and less for engineering references.

A rectangular via in layout turns into an oval shaped via in the actual process of making the via. So you get a width and length to the via. benefit of a rectangular via is that the ECD copper fill process has more margin (effective aspect ratio of the via is reduced) and as such the propensity for forming ECD voids in the via are less. Reliability goes up, lifetime goes up, etc. The downside is the diesize goes up very slightly so as to accommodate the extra bit of metal overlap required to connect the via.

Rectangular vias cause their own process margin issues though when it comes to robust copper-barrier and copper-seed deposition and so it is not uncommon for some IDM's to have eliminated rectangular vias from their design rules, they strictly use square vias (which become round in the process, but they are square in layout).

edit: oh, and I meant to add one clarification...technically via's are only used to connect metal layers in the BEOL (back-end of the line) of an IC. When it comes to connecting the transistors (the FEOL or front-end of the line) to the metal wires in the BEOL those electrical connections are made with what are called "contacts".

Currently we use tungsten metal for the contacts. Future nodes will use copper for the contacts but we aren't there yet. (big, big reliability issue as well as contamination concerns)

And yes, for all the same reasons a layout engineer would judiciously select the locations to implement double (or more) vias the layout engineer (or automated layout software) will place double (or more) contacts.

The spirit of your post remains unchanged, I am merely adding clarification of the technical specifics.

 

[Idontcare]

I have a hard time believing that the media reports on how the GPUs are put together (something I don't fully understand) are any more accurate to reality than those reporting how laser physics (something I do understand) will change the world. i.e. highly complicated things are almost always reported misleadingly or flat or incorrectly.

lol, so true. I was once interviewed by the Dallas Tribune because the US government had granted me and three of my academic colleagues a few million dollar grant to develop 32nm-16nm node ultra-lowk dielectrics.

So the reporter/journalist kept trying to frame his questions in the interview in terms of macro-sized nebulous stuff. "If I held a 32nm chip on my finger would I be able to see it?". Hmmm...the chip itself won't be 32nm dude lol

So naturally, as you have likely already guessed where this is going, when the article came out in the newspaper I was immediately doing a forehead slap as the guy attributes a quote to me saying something utterly absurd like "nanometer sized chips are the future of the industry".

Of course TI marketing contacted the paper and asked for a correction, which they printed, but who reads corrections? I just prayed that no one of any consequence in the industry read that article.

I try and avoid judging a professor or industry professional for the statements attributed to them by an article published in a non-refereed journal...way to much creative engineering of the quotes and context goes on