WCCFAMD Carrizo APU on the 28nm Node Will Have Stacked DRAM On Package

[Erenhardt]

Derp... scratch that
Thanks for the link

 

[Madpacket]

Hopefully AMD gets something out soon using this tech. I suspect we'll get 7750/70 performance for the first release which will kill the $100.00 and under cards. Good stuff!

 

[TrulyUncouth]

Hopefully AMD gets something out soon using this tech. I suspect we'll get 7750/70 performance for the first release which will kill the $100.00 and under cards. Good stuff!

I think their smartest play would be to throw it all behind regaining some mobile market share, plus personally I am most interested in a boost in laptop GPU performance since you pay so much for so little in that space.

 

[frozentundra123456]

Yea, even if they solve the bandwidth problem, I think performance will still trail discrete in the desktop, especially since hopefully new 20 nm cards will be out by then. However if they can get 7750 or 7770 performance in a 600.00 laptop with decent thermals, that would be a very tempting buy.

 

[Abwx]

So basically Intel is saying that there is little point in having more than 32 MB.

For their IGP....

 

[DrMrLordX]

Why would it make the max clock frequency of Carrizo lower?

Target TDP for Carrizo is currently 65W if I recall correctly. That's a power budget that's already 35W lower than the top-end Kaveri chip, and it's the same process node (or it appears to be, anyway). On top of that, they're putting a high-performance bank of stacked DRAM inside the package which is going to be taking up its own likely-small-but-significant slice of that power budget. That doesn't leave much to the CPU or iGPU.

If AMD manages improvements similar to what they achieved in their transition from C2 stepping K10.5 to R0 stepping K10.5 (yes, I am skipping over C3 here), then yes, I could totally see Kaveri-like clockspeeds at 65W TDP. AMD managed some pretty amazing results with R0, such as the 95W 1055T. However, I'm not holding my breath waiting for that.

Failing massive improvements in performance/watt, I just don't see Carrizo shedding 35W from its power budget, adding a big cache, improving IPC (this is Excavator after all), AND maintaining or improving upon Kaveri's available clockspeeds. I certainly don't think this will be a great overclocking chip.

It would be nice if AMD were to prove me wrong, though.

 

[NostaSeronx]

For their IGP....

I've been doing research and the Iris lineup from Intel. Is pretty close to AMD's Kaveri as it supports;

DirectX 12
OpenCL 1.2 (OpenCL 2.0, hint? *wink*)
OpenGL 4.4

It also has QuickSync which is like AMD's VCE and the ability to decode JPEGs and H.264. It probably can run Kaveri's OpenCL H.265 decoder as well.

Broadwell in the Niche Desktop and Laptop and Skylake in the Everything Desktop and Mobile. Would essentially destroy AMD's and Nvidia's GPU advantage if they plan to do 28-nm one more time.

GM107 / Bonaire <<< 5th Gen and 6th Gen, Iris and Iris Pro, will destroy these cards and possibly their successors as well.

The only way AMD can jump ahead in graphics is to adopt HBM. Go 20-nm LPM and adopt AVFS. Then, go for dense streamlined high performance macros.

Basically, with Carrizo AMD has a huge checklist;
- Acquire Higher Power Efficiency.
- Acquire Higher Performance.
- Adopt AVFS for HVM.
- Adopt HBM for fast near memory.
- Jump to 20-nm LPM for HVM.
- Implement Integrated Voltage Regulator.
- Design smart and aggresively.

It would be in our best interests if we don't see engineering samples till after Skylake launches.

 

[Abwx]

I've been doing research and the Iris lineup from Intel. Is pretty close to AMD's Kaveri as it supports;

DirectX 12
OpenCL 1.2 (OpenCL 2.0, hint? *wink*)
OpenGL 4.4

Ivy bridge officialy support DX11 but it was proved in this very forum that shaders werent working accordingly and that the FPS targets were reached
thanks to interpolation with poor image quality in games.

Dont know for HW but i just wanted to point that support and compatibility are two different things.

 

[cbn]

Target TDP for Carrizo is currently 65W if I recall correctly. That's a power budget that's already 35W lower than the top-end Kaveri chip, and it's the same process node (or it appears to be, anyway). On top of that, they're putting a high-performance bank of stacked DRAM inside the package which is going to be taking up its own likely-small-but-significant slice of that power budget. That doesn't leave much to the CPU or iGPU.

If AMD manages improvements similar to what they achieved in their transition from C2 stepping K10.5 to R0 stepping K10.5 (yes, I am skipping over C3 here), then yes, I could totally see Kaveri-like clockspeeds at 65W TDP. AMD managed some pretty amazing results with R0, such as the 95W 1055T. However, I'm not holding my breath waiting for that.

Failing massive improvements in performance/watt, I just don't see Carrizo shedding 35W from its power budget, adding a big cache, improving IPC (this is Excavator after all), AND maintaining or improving upon Kaveri's available clockspeeds. I certainly don't think this will be a great overclocking chip.

It would be nice if AMD were to prove me wrong, though.

Maybe they will raise the TDP.

P.S. Wasn't there some talk or commentary in one of the old articles of an APU with a larger amount of CUs?

 

[HurleyBird]

I wonder if it will be able to boot without memory sticks? Could make some issues easier to diagnose and open up some interesting form factors.

 

[DrMrLordX]

Maybe they will raise the TDP.

They could, for desktop parts. With AMD lately, it's hard to be sure what they'll do.

P.S. Wasn't there some talk or commentary in one of the old articles of an APU with a larger amount of CUs?

I . . . don't know. There has been a lot of talk about what Carrizo is or isn't going to be. Assuming AMD pushes it out in Q1 2015, it shouldn't be too much longer before we know more.

I wonder if it will be able to boot without memory sticks? Could make some issues easier to diagnose and open up some interesting form factors.

That would be a cool feature, though I suspect it would be up to the mobo manufacturers to implement something like that. Technically, simple diagnostic tools should fit in the L2 or L3 of some modern chips. You could load MS-DOS in the L3 of my "unlocked" x2 220 . . . it has more L3 than my 386 had RAM. It still won't boot without memory sticks.

 

[frozentundra123456]

Yea, before we get carried away, all this is just speculation at this point. Hopefully for AMD, the launch will go smoother than Kaveri, where the mobile launch was much later than desktop, and I dont think there is much availability in mobile even yet. Like I said earlier, unless they make a huge improvement, mobile is the place where I see that APUs can shine. Desktop, not so much.

 

[NostaSeronx]

Oh snap! The cross license agreement ends November 11, 2014.

There has been a lot of talk about what Carrizo is or isn't going to be. Assuming AMD pushes it out in Q1 2015, it shouldn't be too much longer before we know more.

AMD's low power lineup is 20-nm with Puma+ and LP Cortex-A57. It would seem everything is going for lower power including Excavator. Which has already joined up in the LP groups work. Tskin and Adaptive Clocking are both works from the Low Power initiative at AMD. The next work for them is Integrated Voltage Regulation and Adaptive Voltage Frequency Scaling.

It would fit very nicely for the APU SoC lineup and the CPU SoC lineup would be all 20-nm. The GPUs are getting the head start since they have more portable designs.

http://images.anandtech.com/doci/7974/Screen-Shot-2014-04-29-at-1.08.08-AM.jpg

Still wondering what that August-October and beyond device will be.

 

[AtenRa]

Yea, before we get carried away, all this is just speculation at this point. Hopefully for AMD, the launch will go smoother than Kaveri, where the mobile launch was much later than desktop, and I dont think there is much availability in mobile even yet. Like I said earlier, unless they make a huge improvement, mobile is the place where I see that APUs can shine. Desktop, not so much.

Yes i could only find a single model in Newegg

Lenovo Z50 with Kaveri A10-7300

• AMD A-Series A10-7300 (1.90GHz)
• 8GB Memory 1TB HDD
• AMD Radeon R6 Series
• 1366 x 768
• Windows 8.1
• DVDRW

$579,99

 

[NTMBK]

How big does it have to be? The Anandtech article on Crystalwell Intel said that:

"There&#8217;s only a single size of eDRAM offered this generation: 128MB. Since it&#8217;s a cache and not a buffer (and a giant one at that), Intel found that hit rate rarely dropped below 95%. It turns out that for current workloads, Intel didn&#8217;t see much benefit beyond a 32MB eDRAM however it wanted the design to be future proof. Intel doubled the size to deal with any increases in game complexity, and doubled it again just to be sure."

So basically Intel is saying that there is little point in having more than 32 MB.

It depends on what you expect to be cached within that buffer. 32MB is an absolute tiny quantity these days in the grand scheme of things. You can barely fit a couple of rendering targets in there. Just a 1080p RGB24 color buffer plus an FP16 Z-buffer would put you up to almost 10MB of memory, and those are some seriously low fidelity buffers.

(Incidentally, this is apparently the reason that so many XBox One games are coming in with <1080p resolutions. Drop the resolution and your render targets are smaller, and easier to fit into the ESRAM.)

But with a buffer that small, you are effectively guaranteeing that none of your models or textures are going to fit into that small cache, and will have to come over your slow DDR3. With a 1GB cache much more of your working set will fit into that cache, and the majority of your memory reads will be coming in at that higher speed. Heck, my current GPU only has 1GB VRAM...

 

[bunnyfubbles]

How big does it have to be? The Anandtech article on Crystalwell Intel said that:

"There’s only a single size of eDRAM offered this generation: 128MB. Since it’s a cache and not a buffer (and a giant one at that), Intel found that hit rate rarely dropped below 95%. It turns out that for current workloads, Intel didn’t see much benefit beyond a 32MB eDRAM however it wanted the design to be future proof. Intel doubled the size to deal with any increases in game complexity, and doubled it again just to be sure."

So basically Intel is saying that there is little point in having more than 32 MB.

for what is essentially a massive L4 cache, sure, its enough, but as an entire video buffer for gaming the dream would be to have enough for ~1080p 3D without having to hit the RAM, and current dGPUs are already averaging 2GB...so yeah, 128MB would be far from enough.

32MB is enough for 1920x1080 @ 32bit color (requires ~8MB of memory, so plenty of room for double or triple buffer), Intel was just thinking ahead and preparing for the advent of 4K (or 4x rather) screens when they decided to quadruple Crystalwell from an already 'adequate' 32MB.

 

[NTMBK]

32MB is enough for 1920x1080 @ 32bit color (requires ~8MB of memory, so plenty of room for double or triple buffer)

Start adding in things like Z buffers and G buffers, and see how far that 32MB gets you...

 

[ShintaiDK]

There is also day and night difference on the cache design capabilties of AMD vs Intel. Plus they use a different cache design as well. So its silly to make a direct compare.

 

[witeken]

Intel on Crystalwell.

 

[ShintaiDK]

As mentioned before. There is nothing pointing to HBM on AMDs roadmap for its next CPU.

Also the second question rises, if its even possible to make a FM1/FM2/FM2+ sized CPU with HBM on 28nm. Or if the socket would have to be bigger. We know for example that Haswell GT3e cant fit on a LGA1150 socket. Only the 14nm Broadwell will allow that.

TSMC for example doesnt even expect tapeout of the first HBM device before Q4 2014. So thats more like a 2016 target at best.

 

[NTMBK]

Also the second question rises, if its even possible to make a FM1/FM2/FM2+ sized CPU with HBM on 28nm. Or if the socket would have to be bigger. We know for example that Haswell GT3e cant fit on a LGA1150 socket. Only the 14nm Broadwell will allow that.

A very good point. There's not a whole lot of room under that heatspreader:

If they wanted to do it, they would either need a new socket or they would only do it on soldered down MBs. Unless they drastically shrunk Carrizo's size somehow.

 

[USER8000]

A very good point. There's not a whole lot of room under that heatspreader:

If they wanted to do it, they would either need a new socket or they would only do it on soldered down MBs. Unless they drastically shrunk Carrizo's size somehow.

According to the WCCFtech article,Carrizo is smaller than Kaveri(!). I wonder if the HDLs AMD was talking about are being used for Excavator??

 

[ShintaiDK]

Btw, GloFo isnt ready either:

 

[NostaSeronx]

The next APU socket should be something close to socket G3.

Btw, GloFo isnt ready either

GlobalFoundries has been ready for 3 years. It is only just now that they started to go into HVM with TSVs.

 

[USER8000]

I saw this on SA forums:

http://www.skhynix.com/inc/pdfDownl.../Databook/Databook_3Q'2014_GraphicsMemory.pdf

Hynix lists HBM availability as current.