[WCCF] Intel Skylake 2015 Platform Details Revealed

[jdubs03]

What is this ratio thing I've never heard of before?


Broadwell was actually slightly faster.

http://www.extremetech.com/computing/171477-intels-14nm-milkshake-its-better-than-yours

There you go.

They are at LEAST 2x now, so Atom has a room to improve without violating what Intel wants.

If we're comparing Haswell-U to BayTrail Z3770 then yes, this holds true, it would probably be about 2.5x in single-thread, but for Haswell-Y the ratio is about 2-to-1.

My guess is, the ratio between Core and Atom will be focused on top-end Atom vs. low TDP-Core.

 

[Pheesh]

The ambiguity in consistency of release schedule when factored by market segment is all due to OEM driven feedback and has little to do with Intel's capability.

Huh, that's a bold conspiracy theory. Okay I'll entertain it, let's see how you justify it.

We are witnessing the results of what happens when a near monopoly enters into an optimized "tidal lock" with its customers (the OEMs, not us end-users) where the tail wags the dog.

Intel listens, and rightfully so, to what its customers are telling it to do when it comes to inventory, production volumes, and release timelines.

What this creates, from our limited visibility, is a seemingly disjointed chaotic release schedule.

Monopoly...what's Intel's mobile market share again?
Okay, so your theory is that all of these OEM's that are competing with eachother are colluding as a group in advising Intel to artificially delay their next gen product even though this would give the OEM's who can bring it to market first a HUGE a competitive advantage in the marketplace over others, and Intel, who has every possible incentive to push out better performance/watt processors to try and gain market share in mobile/tablet markets are just going to put on the brakes on their next gen process, because who cares about profits/market share/the ARM threat/competitive position and shareholders, right?

I think Occam's razor applies here.

 

[Homeles]

And I am more and more inclined to believe the "node after revolution" that really brings exciting products for Intel. Remember 90nm and 45nm? They were kinda disappointing. The 65nm and 32nm were pretty awesome though.

Both Intel's 90nm and 45nm were before my time, but I've done my homework on the latter. I disagree that 45nm was disappointing, and rather strongly too. Penryn gave birth to the ultrabook form factor, and Nehalem brought tremendous performance improvements as a result of turbo boost, and also tremendous improvements in performance per watt. It was a bigger deal than Sandy Bridge, IMO, and easily outshines Ivy Bridge and Haswell. Haswell is truly great as well, but only in the form factors that can really take advantage of the fine-grained power control.

If you're talking strictly process, I'd argue 45nm and 32nm were very even.

Really, there's a huge difference between you and I. You're clearly a pessimist. I just love technology so much, that I can't really be disappointed. I often am at first, when a product doesn't live up to expectations, but it's very easy for me to see the bright side of things. Generally, even the biggest "mistakes" (P4, Bulldozer) end up resulting in important lessons being learned that would not have been if not for the aforementioned mistakes. Sandy Bridge, for example, took a lot of the "good" from P4. I'd imagine sometime down the road that the good parts of Bulldozer will be used to make an awesome new microarchitecture, if AMD ever lives long enough to deliver it.

I thought you also found a presentation by Kelin Kuhn showing an electrostatic limitation on FinFet that extended to 14nm visa vi frequency scaling. I think it may have been a problem with gate capacitance, but I'm not sure about that. I'm searching for it now, but maybe you can find it faster.

Well, 14nm essentially wouldn't even function as a planar process. FinFETs were a necessity, despite the drawbacks at >1V.

This is probably the presentation you're thinking about: http://download.intel.com/pressroom/pdf/kkuhn/Kuhn_22nm_Device.pdf

The general idea is exactly as I've drawn it. FinFETs change the "slope" of the interaction between voltage and leakage, and voltage and transistor delay. Scaling the transistor dimensions move the plot down the Y axis.

 

[TerryMathews]

And I am more and more inclined to believe the "node after revolution" that really brings exciting products for Intel. Remember 90nm and 45nm? They were kinda disappointing. The 65nm and 32nm were pretty awesome though.

On 90nm, you're confusing the chip for the process. Prescott was disappointing. Dothan was not.

 

[TreVader]

Big jumps from process nodes are over. You will never see another node jump look like 45-32nm. The process lead is bogus anyway look at what it's done for Intel in mobile: pretty much nothing.

 

[Homeles]

Big jumps from process nodes are over. You will never see another node jump look like 45-32nm. The process lead is bogus anyway look at what it's done for Intel in mobile: pretty much nothing.

This is simply untrue. There are big changes ahead. The writing is on the wall, even for TSMC et al.

 

[TreVader]

Then why haven't we seen anything since 32nm? It's been YEARS

 

[Homeles]

Then why haven't we seen anything since 32nm? It's been YEARS

It's been one node. All it takes is for one node, and the sky is falling for you folk.

As for why, you can start by reading what I've written in this thread.

 

[jdubs03]

This is simply untrue. There are big changes ahead. The writing is on the wall, even for TSMC et al.

Agreed, III-V + GAA will be a massive change that is likely to drive higher frequencies, and therefore performance. I like to think of each node (irrespective of uArch changes) as a step ladder with new improvements in process design have larger leaps than just scaling down.

 

[Homeles]

Agreed, III-V + GAA will be a massive change that is likely to drive higher frequencies, and therefore performance. I like to think of each node (irrespective of uArch changes) as a step ladder with new improvements in process design have larger leaps than just scaling down.

Lately, the advancements have been compounding. Prior to strained silicon, the only knob you could turn to boost transistor performance was to shrink them. That stopped working. However, there have been so many more dials added. Strained silicon came first, then HKMG, then transistor "shaping."

Now, you improve a little on the strain, and a little on the dielectric, and a little on the transistor design... and you get a pretty big boost.

14nm is probably going to be the biggest improvement Intel has had in quite some time. The density is more than doubling (2.2x or so), the performance and power improvements will be above average. Intel's claims for their 45nm process were "~30% reduction in transistor switching power" and ">20% improvement in transistor switching speed" over their 65nm process. Intel's numbers for their 14nm process are 67% reduced power and 40% increased performance over 22nm.

This is all contingent on whether or not Intel's telling the truth, or cherry picking of course, but thus far they've been fairly honest, from my perspective. I'm still stumped as to what miracles they've managed to work to make these breakthroughs, but they're insistent on keeping quiet.

Also, for any of these claims I'm making, I can provide upon request. For direct quotes, just copy paste the quote into google and click the first PDF you find.

One last bit: the "post-silicon era" is coming. Applied materials stated last June that the likely introduction for SiGe would be at the 10nm or 7nm node, and Imec has stated 10nm as well as of this January, and I think this isn't Intel exclusive. Idontcare probably is legally bound not to comment on that, though

 

[Ajay]

Well, 14nm essentially wouldn't even function as a planar process. FinFETs were a necessity, despite the drawbacks at >1V.

This is probably the presentation you're thinking about: http://download.intel.com/pressroom/pdf/kkuhn/Kuhn_22nm_Device.pdf

The general idea is exactly as I've drawn it. FinFETs change the "slope" of the interaction between voltage and leakage, and voltage and transistor delay. Scaling the transistor dimensions move the plot down the Y axis.

Yes, that's the paper. I guess was a bit confused. Capacitance is covered on pp. 32-36, where at one point Cfringe in MuGFETs are said to be higher than planar and then lower. It's actually lower due to limitations in place during manufacturing

MuGFET has DECREASED epi-facet to poly capacitance due to facet limited fin growth

That same presentation briefly covers III-V materials. Since post 14nm, Vdd will be going down, III-V materials are needed to be employed to improve Ion at the cost of a higher leakage current. We'll have to see what Intel does to reduce I_leak and reduce heat output.

Going back to 14nm: if the chart from Intel is correct, the die size will drop ~54% (probably less, since the iGPU will be using more xtors) and the power will drop ~67% seems to indicate that 14nm CPUs will run a bit cooler than 22nm parts. If that turns out to be the case, there may very well be some extra frequency headroom, at least for overclockers (dependent on how well the IHS works for desktop parts).

 

[IntelUser2000]

On 90nm, you're confusing the chip for the process. Prescott was disappointing. Dothan was not.

65nm and 32nm chips "broke ground". It enabled x86 phone chips to be possible(Medfield), dramatically improved perf/watt on Notebooks(Sandy Bridge), and brought the much-famed Core 2.

Nehalem was a good chip, but it wasn't uniformly well received. I remember there was an argument about how Nehalem brought minimal single-thread increases and the usefulness of the extra threads brought on by SMT. While there's a design aspect as well, I don't doubt there is process, the "Tick Tock" involved. They skipped "Larrabee", and 45nm version of Itanium didn't exist.

The entire company seems to be on that "cycle". It's looking like 14nm is yet another good one. While no one knows how 10nm will be, I wouldn't bet too much based on how 22nm products turned out to be.

Maybe there is a genuine reason for it. The first generation of "revolution" like Strained Silicon, HKMG, and TriGate has risks on the process, so naturally there are kinks to be worked on.

Intel's numbers for their 14nm process are 67% reduced power

Homeles, this is why I say everyone spins, including Intel, which you are very optimistic of.

Take a closer look at the power graph. The left side of the bar is labeled "Switching Energy Change(%)". The part that Intel labeled "67% drop", it goes from slightly under 75% to approximately 0%. My guess is "0%" is really "1x" and "75%" is really "1.75x".

The "67% drop" literally means x % - 67%. That could be 75-67, 67-67, any combination that complies with the graph.

That's roughly 40% drop, coinciding with their demo of Broadwell-Y that it uses 35-40% less power at same performance.

 

[witeken]

The entire company seems to be on that "cycle". It's looking like 14nm is yet another good one. While no one knows how 10nm will be, I wouldn't bet too much based on how 22nm products turned out to be.

Extrapolation is nice, but with all those various solutions that are being implemented, I don't think there's any reliable thing to extrapolate. The result of using post-silicon materials is going to be very different from making the gate better or implementing HK/MG, so any pattern you might see, in my opinion, is probably just random luck.

Maybe there is a genuine reason for it. The first generation of "revolution" like Strained Silicon, HKMG, and TriGate has risks on the process, so naturally there are kinks to be worked on.

Yeah, but intuitively, you'd think that a new technology like FinFET brings tremendous improvements, less than an iteration of the technology.

 

[TuxDave]

Take a closer look at the power graph. The left side of the bar is labeled "Switching Energy Change(%)". The part that Intel labeled "67% drop", it goes from slightly under 75% to approximately 0%. My guess is "0%" is really "1x" and "75%" is really "1.75x".

The "67% drop" literally means x % - 67%. That could be 75-67, 67-67, any combination that complies with the graph.

That's roughly 40% drop, coinciding with their demo of Broadwell-Y that it uses 35-40% less power at same performance.

"Switching energy" is a dynamic power when only looking at very local gate and parasitic capacitance. However, total power consumption is a sum of leakage, switching energy at the local level and switching energy at a larger global level. On top of ALL that, you have architectural changes, frequency targets and final process decisions.

I would be surprised if anyone could take transistor level switching energy to derive the final power of a future product. But other than the math part of your discussion, you're right. Everyone spins. The way I look at it, all numbers and facts are based on SOME data point (I give the benefit of the doubt that they didn't just make up a number). Whether or not that number is important is the amount of "spin" the marketing team can put on it.

Edit: And just to clarify, switching energy IS actually a useful metric. However, it's not the end-all-be-all of metrics.

 

[coercitiv]

That's roughly 40% drop, coinciding with their demo of Broadwell-Y that it uses 35-40% less power at same performance.

The Broadwell-Y demo showed up to 30% drop in power usage at normalized performance.(4.9W vs 6.8W as shown in the video)

 

[jdubs03]

The Broadwell-Y demo showed up to 30% drop in power usage at normalized performance.(4.9W vs 6.8W as shown in the video)

Indeed, but it was also reported that the run of Cinebench finished quicker on Broadwell-Y at those levels, and it is early silicon so improvements from then to now could easily occur to raise that 30% to 35+%. And at various times during the demonstration the reduction was more than 30%.

 

[Ajay]

"Switching energy" is a dynamic power when only looking at very local gate and parasitic capacitance. However, total power consumption is a sum of leakage, switching energy at the local level and switching energy at a larger global level. On top of ALL that, you have architectural changes, frequency targets and final process decisions.

Ugh, I hate marketing slides :| Anyway, good point, we have no idea what the total power usage will be, and hence, no idea what the final W/cm2 will be. No way to even guess if there is headroom for higher frequencies or not.

 

[Homeles]

Homeles, this is why I say everyone spins, including Intel, which you are very optimistic of.

Take a closer look at the power graph.

"Switching energy" is a dynamic power when only looking at very local gate and parasitic capacitance. However, total power consumption is a sum of leakage, switching energy at the local level and switching energy at a larger global level. On top of ALL that, you have architectural changes, frequency targets and final process decisions.

I would be surprised if anyone could take transistor level switching energy to derive the final power of a future product. But other than the math part of your discussion, you're right. Everyone spins. The way I look at it, all numbers and facts are based on SOME data point (I give the benefit of the doubt that they didn't just make up a number). Whether or not that number is important is the amount of "spin" the marketing team can put on it.

Edit: And just to clarify, switching energy IS actually a useful metric. However, it's not the end-all-be-all of metrics.

Thanks for pointing out my mistake.

 

[IntelUser2000]

"Switching energy" is a dynamic power when only looking at very local gate and parasitic capacitance. However, total power consumption is a sum of leakage, switching energy at the local level and switching energy at a larger global level. On top of ALL that, you have architectural changes, frequency targets and final process decisions.

Thank you.

Perhaps that's why Broadwell's gain is somewhat less, because leakage doesn't go down as much.

Thanks for pointing out my mistake.

You are welcome. Accurate information is always good.

 

[TuxDave]

Ugh, I hate marketing slides :| Anyway, good point, we have no idea what the total power usage will be, and hence, no idea what the final W/cm2 will be. No way to even guess if there is headroom for higher frequencies or not.

I don't like being the party-pooper when it comes to CPU speculation.

That said, if you're willing to allow a much larger margin of error in your guesses and the fact that engineers are supposed to be rational and that you don't have unlimited time and resources.

Make up a number on the breakdown of power and what process may give you, make a guess on the frequency target, make up some random number for architectural improvements (whatever is on the latest rumor vines), you can probably can come up with a not THAT bad of a guess. It won't be close to 10% accurate but it's just a guess anyways.

 

[witeken]

Ugh, I hate marketing slides :| Anyway, good point, we have no idea what the total power usage will be, and hence, no idea what the final W/cm2 will be. No way to even guess if there is headroom for higher frequencies or not.

I really don't like that slide. It seems to be made to be confusing, misleading and hazy. I guess Intel's IDF demo is the best indication of what we'll see in term of power consumption: 30% decrease, at least for Broadwell-Y.

 

[Enigmoid]

I really don't like that slide. It seems to be made to be confusing, misleading and hazy. I guess Intel's IDF demo is the best indication of what we'll see in term of power consumption: 30% decrease, at least for Broadwell-Y.

I would say at LEAST 30% efficiency improvements on final silicon.

 

[Idontcare]

Huh, that's a bold conspiracy theory. Okay I'll entertain it, let's see how you justify it.


Monopoly...what's Intel's mobile market share again?
Okay, so your theory is that all of these OEM's that are competing with eachother are colluding as a group in advising Intel to artificially delay their next gen product even though this would give the OEM's who can bring it to market first a HUGE a competitive advantage in the marketplace over others, and Intel, who has every possible incentive to push out better performance/watt processors to try and gain market share in mobile/tablet markets are just going to put on the brakes on their next gen process, because who cares about profits/market share/the ARM threat/competitive position and shareholders, right?

I think Occam's razor applies here.

Not sure what exactly you are railing against here, this is standard supply-chain management type stuff that I'm discussing.

If that is tantamount to a "conspiracy theory" for you, then I'm guessing you don't have much experience with Intel's supply chain?

AMD does this as well, coordinating with OEMs regarding their launch timelines for their next gen products by market segment within the context of managing existing inventory at the OEMs.

 

[Idontcare]

I don't like being the party-pooper when it comes to CPU speculation.

That said, if you're willing to allow a much larger margin of error in your guesses and the fact that engineers are supposed to be rational and that you don't have unlimited time and resources.

Make up a number on the breakdown of power and what process may give you, make a guess on the frequency target, make up some random number for architectural improvements (whatever is on the latest rumor vines), you can probably can come up with a not THAT bad of a guess. It won't be close to 10% accurate but it's just a guess anyways.

I'll take a stab at guessing - a 5-6% improvement in Fmax an 8-10% increase in IPC/thread at normalized Vnom, Pmax, and TJmax.

 

[IntelUser2000]

I'll take a stab at guessing - a 5-6% improvement in Fmax an 8-10% increase in IPC/thread at normalized Vnom, Pmax, and TJmax.

For Broadwell or Skylake?

For Broadwell, I'd expect pretty much nothing in terms of IPC gain. We didn't see one in Westmere either, remember? For Skylake, that sort of improvement will be a disappointment at the least.