Ajay
Lifer
- Jan 8, 2001
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28nm should really increase the xtor budget AMD had for the design engineers.
The clockspeeds should be improved, 28nm being higher Idrive than 32nm, and I'd expect dynamic power to be lowered over that of 32nm as well. But I'd expect static leakage to be higher (or at best, no worse) than 32nm because they won't have SOI to assist them in lowering substrate leakage at 28nm.
So depending on what they do with their power-consumption budget and xtor budget, we'll either get something on the order of 20% higher IPC but no faster clockspeed (they throw all the xtors towards bolstering IPC), or they'll keep it lean and clean and push for 5GHz+ clockspeeds (small die, IPC not much better than PD, but higher clocks from the power-budget).
The problem is they are coming out late even for 28nm with Steamroller. 28nm has been out now for what, 18 months? AMD really needs steamroller to be on TSMC 20nm IMO with a roadmap to porting it to 16nm w/FinFet. At GloFo they simply have no future.
Really, higher Idrive with a narower gate?
Do bulk xtors pack better than SOI, or are we talking about an ~25% gain in xtors?
I can't imagine AMD going for that high a clock; SS would need to be very steep and hence off current too high (although putting 5GHz! on a box would be good for mass marketing - 'think old school' might work). Then again, we haven't gotten much in the way of details on IPC improvements except for MT.
Agree with the last paragraph 900%; having an Albatross tied to a sinking ship would give any captain heartburn!