Thoughts on "8 Core" Bulldozer and "4 Core Sandy Bridge"

[Nemesis 1]

I really don't understand what you are saying. Not trying to be mean, maybe there is a language translation issue here. I am going to answer your question as best I can since you seemed to end it in middle of a sentence.

Right off the bad EMT64 and SSE are built off of or exact copies of AMD technology. Chances are that AMD owns some of the IP in regards to tech used in QPI, IMC, and multiple core integration. But those two alone count for almost every Intel x86 CPU made in the last 10 years. That's over a billion CPU's. But I am not a CPU designer I don't work for AMD or Intel so I can read off a checkbox for it. But you go back to before 1998, and any technology Intel was using wasn't from AMD. (Though the original Pentium up to an including the Core 2 Quad, used GTL which was licensed from another company). In 10 years from 0 to now over 1 billion CPU's using AMD technologies.

I really don't understand why you are comparing me to a snake and calling me mean and sneaky. The information I am giving you is understood throughout the PC industry.

I will give ya AMD 64 thats all.

You said Intel copyied Exact copies which is not a fact or true .

In computing, Streaming SIMD Extensions (SSE) is a SIMD instruction set extension to the x86 architecture, designed by Intel and introduced in 1999 in their Pentium III series processors as a reply to AMD's 3DNow! (which had debuted a year earlier). SSE contains 70 new instructions, most of which work on single precision floating point data. SIMD instructions can greatly increase performance when exactly the same operations are to be performed on multiple data objects. Typical applications are digital signal processing and graphics processing.

Intel's first IA-32 SIMD effort, was the MMX instruction set. MMX had two main problems: it re-used existing floating point registers making the CPU unable to work on both floating point and SIMD data at the same time, and it only worked on integers. SSE floating point instructions operate on a new independent register set (the XMM registers), and it adds a few integer instructions that work on MMX registers.

SSE was subsequently expanded by Intel to SSE2, SSE3, SSSE3, and SSE4. Because it supports floating point math, it had a wider application than MMX and became more popular. The addition of integer support in SSE2 made MMX largely redundant, though further performance increases can be attained in some situations by using MMX in parallel with SSE operations.

SSE was originally known as KNI for Katmai New Instructions (Katmai being the code name for the first Pentium III core revision). During the Katmai project Intel was looking to distinguish it from their earlier product line, particularly their flagship Pentium II. It was later renamed ISSE, for Internet Streaming SIMD Extensions, then SSE. AMD eventually added support for SSE instructions, starting with its Athlon XP and Duron (Morgan core) processors.

I didn't call you a snake or any other name . Notice the period behind the defiition

I won't even bother with the rest of your nonsense

 

[Abwx]

SSE was subsequently expanded by Intel to SSE2, SSE3, SSSE3, and SSE4. Because it supports floating point math, it had a wider application than MMX and became more popular. The addition of integer support in SSE2 made MMX largely redundant, though further performance increases can be attained in some situations by using MMX in parallel with SSE operations.

The only purpose of SSE2 FP was to regain floating point perf crown
since intel Was devastated by AMD s superiority in X87...

As for intel s great innovations in instructions, keep on dreaming..
Basically, intel went as far as rebranding existing instructions in AMD s
3D now and sell the repackaged thing as its own finding..

The earlier SIMD instruction sets on the x86 platform, from oldest to newest, are MMX, 3DNow! (developed by AMD), SSE and SSE2.

One advantage of 3DNow! is that it is possible to add or multiply the two numbers that are stored in the same register. With SSE, each number can only be combined with a number in the same position in another register. This capability, known as horizontal in Intel terminology, was the major addition to the SSE3 instruction set.

:biggrin:

http://en.wikipedia.org/wiki/3DNow!

 

[Topweasel]

Since we are referencing Wikipedia, but the best info is from business an enthusisiasts mags from the late 90's. But guessing from you posting you are to young to have read them or didn't have access to them.

The first implementation of 3DNow! technology contains 21 new instructions that support SIMD floating-point operations. The 3DNow! data format is packed, single-precision, floating-point. The 3DNow! instruction set also includes operations for SIMD integer operations, data prefetch, and faster MMX-to-floating-point switching. Later, Intel would add similar (but incompatible) instructions to the Pentium III, known as SSE for Streaming SIMD Extensions.

 

[LOL_Wut_Axel]

I've been in IT for over 25 years.

I know how it works, thanks.

You clearly don't, as you took marketing words and tried to apply them to the roadmap.

Bulldozer is not a Mainstream CPU; Llano is. Brazos is Essential (low-end). Bulldozer and Sandy Bridge are Performance CPUs. Sandy Bridge-E is Enthusiast, but there will not be no competition for it from AMD.

 

[Nemesis 1]

Since we are referencing Wikipedia, but the best info is from business an enthusisiasts mags from the late 90's. But guessing from you posting you are to young to have read them or didn't have access to them.

The first implementation of 3DNow! technology contains 21 new instructions that support SIMD floating-point operations. The 3DNow! data format is packed, single-precision, floating-point. The 3DNow! instruction set also includes operations for SIMD integer operations, data prefetch, and faster MMX-to-floating-point switching. Later, Intel would add similar (but incompatible) instructions to the Pentium III, known as SSE for Streaming SIMD Extensions.

OK you win . ALL this is a lie.

SSE contains 70 new instructions, most of which work on single precision floating point data. SIMD instructions can greatly increase performance when exactly the same operations are to be performed on multiple data objects. Typical applications are digital signal processing and graphics processing.

Intel's first IA-32 SIMD effort, was the MMX instruction set. MMX had two main problems: it re-used existing floating point registers making the CPU unable to work on both floating point and SIMD data at the same time, and it only worked on integers. SSE floating point instructions operate on a new independent register set (the XMM registers), and it adds a few integer instructions that work on MMX registers.

 

[Nemesis 1]

The only purpose of SSE2 FP was to regain floating point perf crown
since intel Was devastated by AMD s superiority in X87...

As for intel s great innovations in instructions, keep on dreaming..
Basically, intel went as far as rebranding existing instructions in AMD s
3D now and sell the repackaged thing as its own finding..

:biggrin:

http://en.wikipedia.org/wiki/3DNow!

YA so Its just an extension of intel MMX Hows 3D holding up . How did it do in benchmarks Against SSE 2 3D now is an extension of MMX the first Simd instruction set.

The next Thing you guys be saying Intel riped off SSE5 and FMA3 from AMD because AMD changed its mind and went FMA 4 instead . and AMD invented AVX.

Where are the extensions to 3Dnow???? 3D Now is basicly dead . Just legacy code like MMX taking up space

 

[Abwx]

OK you win . ALL this is a lie.

Intel's first IA-32 SIMD effort, was the MMX instruction set. MMX had two main problems: it re-used existing floating point registers making the CPU unable to work on both floating point and SIMD data at the same time, and it only worked on integers. SSE floating point instructions operate on a new independent register set (the XMM registers), and it adds a few integer instructions that work on MMX registers.

The lie is that these limitations were only for intel cpus...
Read again :

One advantage of 3DNow! is that it is possible to add or multiply the two numbers that are stored in the same register. With SSE, each number can only be combined with a number in the same position in another register. This capability, known as horizontal in Intel terminology, was the major addition to the SSE3 instruction set.
A disadvantage with 3DNow! is that 3DNow instructions and MMX instructions share the same register-file, whereas SSE adds 8 new independent registers (XMM0 - XMM7.)
Because MMX/3DNow! registers are shared by the standard x87 FPU, 3DNow! instructions and x87 instructions cannot be executed simultaneously. However, because it is aliased to the x87 FPU, the 3DNow! & MMX register states can be saved and restored by the traditional x87 F(N)SAVE and F(N)RSTOR instructions. This arrangement allowed operating systems to support 3DNow! with no explicit modifications, whereas SSE registers required explicit operating system support to properly save and restore the new XMM registers (via the added FXSAVE and FXRSTOR instructions.)
The FX* instructions are an upgrade to the older x87 save and restore instructions because these could save not only SSE register states but also those x87 register states (hence which meant that it could save MMX and 3DNow! registers too).
On AMD Athlon XP and K8-based cores (i.e. Athlon 64), assembly programmers have noted that it is possible combine 3DNow! and SSE instructions to reduce register pressure, but in practice it is difficult to improve performance due to the instructions executing on shared functional units.[9]

http://en.wikipedia.org/wiki/3DNow!#cite_note-8

 

[Nemesis 1]

The debate was who was first with simd instructions not a nameing scheme .

Because some one is first with something on x86 doesn't mean that someone else didn't go in that direction long befor that . Caned projects that actually had silly.


Timna was the codename of a proposed central processing unit (CPU) family by Intel. The project was announced in 1999 and was designed in Haifa, Israel; "Timna" is also the name of a valley in Israel.

The chip was supposed to be the first CPU with an integrated graphics processing unit (GPU) and random access memory (RAM) controller which was designed to work with the RDRAM type of RAM. The price of RDRAM did not drop as expected by Intel.[citation needed] It was decided to use the Memory Translator Hub (MTH) that is also used by the Intel 820 chipset to link Timna with the SDRAM type of RAM. Later, a serious defect was discovered in the design of the MTH and so the Intel 820 based motherboards using it had to be recalled. The MTH was rebuilt again but problems remained.

Timna was canceled on September 29, 2000. ( Rambus was the problem but now we know that Dram makers munipulated the market for DDR nemesis)

The processor was expected to be clocked from 600 MHz to 700 MHz, use a 133 MHz front-side bus (FSB), have a L2 cache size of 128 KB, and was to be manufactured at a 180 nm process.[1]

Intel Haifa was later tasked to be the backup team for intel's mobile CPU design. Their knowledge of Tinma's P6 derived architecture heavily influenced their project Banias.

 

[Nemesis 1]

Even tho AMD was first to successfully use IMC on x86 they in NO way invented it . Nor can you have a patent on something that is moved ondie , Its still intels memory controller which is better than AMDs. Intel also was first to design for GPU ondie with cpu on x86. All this in 1999 and I mean all of it.

 

[Abwx]

Even tho AMD was first to successfully use IMC on x86 they in NO way invented it . Nor can you have a patent on something that is moved ondie , Its still intels memory controller which is better than AMDs. Intel also was first to design for GPU ondie with cpu on x86. All this in 1999 and I mean all of it.

If intel s timna was such a breakthrough , how is that it was soon canceled ala Larabee ? (yet another big improvement :whiste...

Truth is that since Athlon cpu , AMD brought to X86 most of the innovations
that did matter and all implementations were copied by Intel,
including their recent cpu uarch...

 

[Nemesis 1]

Did you read the link at all and see what they actually referred to as party and what type of topics and wording was used.

Fact is that while Intel is the reigning master of all that is X86, they don't own all of it.

You talk about wording used without the context of the entire contract and expect anyone to buy what your sellin . Not . Than you accuse me of name calling which I never do online. I was defining a word for you . Nothing more nothing less /

Now lets get back to topic since all the off topic has been covered. Even tho the topic is wide in scope. I haven't even gone near reverseHT as you did in another thread . and intel is actually coming with it or its already here and we haven't been told or its up coming. But one thing is for fact ya need great compilers. AMD must have those . Oh wait AMD cries about Intel compilers not working as well with their CPUs as Intels . Intel designs compilers fo Intels Arch not AMD cry me a river. IF amd would supply Intel with early samples of their cpus than maybe intel would help them out . Have you yet backed up your statement that Prefix of VEX is not an intel exclusive and AMD can use it . Does AMD also get intels software to implament Prefix of vex . Does intel have to give AMD its jitcompiler? In the back rooms of intel this type of code is called computational slices and has to be used with software. Intels Software

 

[Abwx]

IF amd would supply Intel with early samples of their cpus than maybe intel would help them out . . Does intel have to give AMD its jitcompiler?

Neither samples nor intel compiler s need to be given to amd;
only that when compiling a soft , intel compilers create routines
that dispatch code according to the Cpu CPUID and not with a test
detecting if genuine intel cpu is on board or not...

http://www.swallowtail.org/naughty-intel.shtml

 

[Nemesis 1]

If intel s timna was such a breakthrough , how is that it was soon canceled ala Larabee ? (yet another big improvement :whiste...

Truth is that since Athlon cpu , AMD brought to X86 most of the innovations
that did matter and all implementations were copied by Intel,
including their recent cpu uarch...

Are you really saying this > I guess so . Your using redherring. Intel had the project back in 1999 , Rambus memory pricies were insane . Intel had know choice . None of that matters . AMD has only innovated 2 things on X86 that was worth while . Point to point and IMC none of which was an AMD invention. They simply put it on die first and used HT first. Intel memory controller is in fact Intels memory controller. Its just ondie .

As far as ht goes . Intels P6 was infact designed with point to point on the die but wasn't implamented We all know when it was and it was only for 2 cores on the orginal PRO.

DEC did more innovating than anybody. If Intel copied AMDS arch . AMD needs to get with there own programm . Cause intel is slapping them around with it. According to some here intel is inferior to AMDs . But Intels is better optimized. What happened to K9 went to doggy heaven. BD 7 years in the making maybe longer.

 

[Nemesis 1]

If intel s timna was such a breakthrough , how is that it was soon canceled ala Larabee ? (yet another big improvement :whiste...

Truth is that since Athlon cpu , AMD brought to X86 most of the innovations
that did matter and all implementations were copied by Intel,
including their recent cpu uarch...

Here some facts . AMD will never be allowed to use prefix of vex because that code works only with intel software and that software has taken years to develop. AMD will never be able to use LRBin again a software layer is involved for that hardware to work . Again years to develop. AMD does not have access to intels jitcompilers or software.

I just posted an 800 page pdf on intel AVX and FMA3 . read it its about the present and future read it now so you don't confuse intels work with AMds.

 

[Nemesis 1]

Neither samples nor intel compiler s need to be given to amd;
only that when compiling a soft , intel compilers create routines
that dispatch code according to the Cpu CPUID and not with a test
detecting if genuine intel cpu is on board or not...

http://www.swallowtail.org/naughty-intel.shtml

Intels hardware and AMDs hardware are not identical . Intel chooses the Best Path for its CPU intel does not have to choose the best path for AMDs CPU as the FTC must have agreeded. As Intel because of the FTC has to pay for any recompiling and not much of that is going on . It would seem 20% market share isn't worth the effort . The FTC remedey. Intel has to tell developers that intels compilers may not give the best performance for cpus other than intel . This was a hugh intel victory. So its business as usual . Intels compilers Intels Cpus Intels money intels research intels PARTY.

 

[podspi]

What software are you even talking about? Are you trying to imply that only Intel's compiler will be able to compile optimized code for Intel's CPUs? Because that sounds like an antitrust issue to me.

And if all compilers can generate optimized code, then that means that it is just an instruction set issue, which we've already established are shared between Intel and AMD.

 

[Nemesis 1]

NO I am saying that AVX is getting recompiled work Ready for the Haswell generation of cores and compilers running morphed x86 software. NO hardware X86. When haswell appears all the sse2&3 code that uses the prefix of vex code correctly well be known New programs should use instruction set that gives best results. Intel can complete the software This is were LRBni comes in and the vector unit comes into play As intel continues to morph X86 code. Everthing intel has done since 1999 has lead in this direction The Elbrus buy out . Intel wanting to do itanic with VLIW What intel was trying to do with the P6, AVX FMA4 announcement . Than saying they would do AVX and the Prefix of vec. Only cancelling FMA4. Larribbee and the development work LRBin with inorder cores and that development continues on inorder cores using a vector Unit TO further development of Vex instruction code along with SB IB and finally the LRBin instruction set running VLIW cpu Morphing X86.legacy code that wouldn't convert VeX instruction set with LRBIN tieing all three elements to gether Jit compilers VEX instruction set Prefix of VEX. compilers

 

[Arachnotronic]

I reeeally want Haswell to come out!

 

[Edrick]

You clearly don't, as you took marketing words and tried to apply them to the roadmap.

Bulldozer is not a Mainstream CPU; Llano is. Brazos is Essential (low-end). Bulldozer and Sandy Bridge are Performance CPUs. Sandy Bridge-E is Enthusiast, but there will not be no competition for it from AMD.

Clearly you seem to be the one who is consumed with the marketing lingo.

News flash, if SB-E and Bulldozer are priced in the same segment, then they will compete with each other. It doesn't matter really what the pre-release roadmaps say.

 

[Edrick]

I reeeally want Haswell to come out!

Agreed!

Ever since I had my Q9400, I told myself I would wait for Haswell. But I have no self control and have upgraded to a i5 750 and a 2500K since then and I plan on getting a SB-E the day they are released.

Intel must love people like me.

 

[Topweasel]

Clearly you seem to be the one who is consumed with the marketing lingo.

News flash, if SB-E and Bulldozer are priced in the same segment, then they will compete with each other. It doesn't matter really what the pre-release roadmaps say.

They are not going to be though. SB-E has been shown on the road map to fill segments that when compared to the previous i7's they are replacing would be priced out of the $320 that the highest BD is getting priced.

 

[hardboy]

Sbe will start arnd 500 600 $ or more for just the cpu and another 300 400 for the mobo

 

[Nemesis 1]

Everthing on Intel AVX is here.

http://software.intel.com/en-us/articles/using-intel-avx-without-writing-avx/

 

[Lepton87]

NO I am saying that AVX is getting recompiled work Ready for the Haswell generation of cores and compilers running morphed x86 software. NO hardware X86. When haswell appears all the sse2&3 code that uses the prefix of vex code correctly well be known New programs should use instruction set that gives best results. Intel can complete the software This is were LRBni comes in and the vector unit comes into play As intel continues to morph X86 code. Everthing intel has done since 1999 has lead in this direction The Elbrus buy out . Intel wanting to do itanic with VLIW What intel was trying to do with the P6, AVX FMA4 announcement . Than saying they would do AVX and the Prefix of vec. Only cancelling FMA4. Larribbee and the development work LRBin with inorder cores and that development continues on inorder cores using a vector Unit TO further development of Vex instruction code along with SB IB and finally the LRBin instruction set running VLIW cpu Morphing X86.legacy code that wouldn't convert VeX instruction set with LRBIN tieing all three elements to gether Jit compilers VEX instruction set Prefix of VEX. compilers

Is anyone else having problems understanding this incoherent gibberish?

 

[Topweasel]

Is anyone else having problems understanding this incoherent gibberish?

I noted it once or twice, words are missing, sentences cut off, its hard to challenge any of the technical information that he posts because its all half there and broken up. If you try, then it always turns out that you read it wrong and he was saying something completely different.

Though as a side comment. If what I barely understand from his posting is correct. Last 3 times Intel has made transitions away from their standard CPU design it has cost them billions and or been perceived as failures. Larrabee, Itanium, Netburst. I wouldn't get to worked up about such a big transition. Just because they are big and have lots of money doesn't mean they can't screw up either.