It occurs to me i may have been misunderstood, perhaps it's my fault, should have expanded further..
Rephrased then:
I used the word 'performance' for a reason.
CCX to CCX (same die), 4 cores at each complex, at same speed, is one thing.
Chip to Chip (
different die), 4 cores at
each die, same speed as above, is or can be another.
Problem 1), attaining the clocks themselves.
Problem 2), attaining relative performance; hence my mentioning the Fabric in the second paragraph. They could all run at 1800X speeds, both scenarios above, but still suffer in the second scenario (MCM) if the die-to-die latency is too high.
2) i) We have no knowledge of whether this is possible yet or not, especially since it's a new stepping, no data.
2) ii) Even if it was, theoretically/in their labs, there's still a chance the cost (power) entailed is so high that AMD has had to compromise with lower performance. Again, we cannot know in advance, divination doesn't work here ^^