The Ryzen "ThreadRipper"... 16 cores of awesome

[ddogg]

it is true - might not have been from Tom's article but a bunch of articles covered it. interesting thing though - im thinking maybe AMD was wanting to get in the door with a big OEM as they have not played in that space in a while and said they would give 1 OEM supply if the others were not biting?

Looks like you're right. The PCworld article said Dell is the only big OEM with rights to sell TR systems this year, but smaller boutique companies will be able to sell it as well as DIY builders.

 

[raghu78]

Threadripper 1950x 16C/32T - 3.4 Ghz base , 3.7 Ghz boost

http://wccftech.com/amd-ryzen-threadripper-1950x-specs-performance-leak/
https://browser.primatelabs.com/v4/cpu/3097893

Multithread scaling is inferior to Intel Xeons in GB4 . But still performance is pretty good. If pricing comes in at USD 999 AMD will shakeup high end enthusiast and quite a bit of even the low end server market.

 

[Ancalagon44]

Threadripper 1950x 16C/32T - 3.4 Ghz base , 3.7 Ghz boost

http://wccftech.com/amd-ryzen-threadripper-1950x-specs-performance-leak/
https://browser.primatelabs.com/v4/cpu/3097893

Multithread scaling is inferior to Intel Xeons in GB4 . But still performance is pretty good. If pricing comes in at USD 999 AMD will shakeup high end enthusiast and quite a bit of even the low end server market.

Look at the memory clockspeed of the TR compared to the Xeon - the Xeon is running at a higher memory clock.

And we all know how sensitive Zen is to memory clockspeed since it also determines the speed of the infinity fabric.

EDIT: Looks fake - look at the L3 cache. Notice the 32768 kb x 4. If you look at the previous lines, they have x 16, which is correct. 512kb x 16, for example, which is correct. But, 32768kb x 4 is not correct, it is 32768kb total. AMD has said that the highest end models will have 40mb of memory, therefore the L3 cache cannot be 32768kb x 4, it must be 32768kb total, or 8192kb x 4.

 

[raghu78]

Look at the memory clockspeed of the TR compared to the Xeon - the Xeon is running at a higher memory clock.

And we all know how sensitive Zen is to memory clockspeed since it also determines the speed of the infinity fabric.

EDIT: Looks fake - look at the L3 cache. Notice the 32768 kb x 4. If you look at the previous lines, they have x 16, which is correct. 512kb x 16, for example, which is correct. But, 32768kb x 4 is not correct, it is 32768kb total. AMD has said that the highest end models will have 40mb of memory, therefore the L3 cache cannot be 32768kb x 4, it must be 32768kb total, or 8192kb x 4.

Good point. Ryzen TR supports DDR4 memory speeds up to 2933 Mhz whereas the GB benchmark was done at 2133 Mhz. I agree that Ryzen benefits a lot from higher memory clock speeds as the Infinity Fabric runs at half the memory speed.

 

[dnavas]

Threadripper 1950x 16C/32T - 3.4 Ghz base , 3.7 Ghz boost

http://wccftech.com/amd-ryzen-threadripper-1950x-specs-performance-leak/
https://browser.primatelabs.com/v4/cpu/3097893

Multithread scaling is inferior to Intel Xeons in GB4 . But still performance is pretty good. If pricing comes in at USD 999 AMD will shakeup high end enthusiast and quite a bit of even the low end server market.

Umm, those scores are 1700-level, so, if you feel the multithread scaling is "pretty good" get yourself a 1700 and rest easy. In fact, a 1700 should give you better single-core result than this, even. I wonder what the progenitor of this set of scores really was, because even a 1700 should win out: https://browser.primatelabs.com/v4/cpu/2844244

 

[swilli89]

Threadripper 1950x 16C/32T - 3.4 Ghz base , 3.7 Ghz boost

http://wccftech.com/amd-ryzen-threadripper-1950x-specs-performance-leak/
https://browser.primatelabs.com/v4/cpu/3097893

Multithread scaling is inferior to Intel Xeons in GB4 . But still performance is pretty good. If pricing comes in at USD 999 AMD will shakeup high end enthusiast and quite a bit of even the low end server market.

Just an FYI similar bogus scores were reported by the same source for Ryzen ahead of its own release. Keep in mind that multi-core score is equiavalent to about 6 cores with perfect scaling... I say wait for better sources of TR performance.

 

[lolfail9001]

EDIT: Looks fake - look at the L3 cache. Notice the 32768 kb x 4. If you look at the previous lines, they have x 16, which is correct. 512kb x 16, for example, which is correct. But, 32768kb x 4 is not correct, it is 32768kb total. AMD has said that the highest end models will have 40mb of memory, therefore the L3 cache cannot be 32768kb x 4, it must be 32768kb total, or 8192kb x 4.

Geekbench messes up with Ryzen 7 cache too, it reports 16MB x2 for R7 1700, for example. Simply it reports total cache x amount of blocks, instead of cache per block x amount over blocks.

Anyways, that score looks sincerely bogus, so for time being i will consider it either a fake or some weird Geekbench issue.

Though it has to be noted that geekbench multi core scaling is anything but linear so you have to look at subscores that are not available.

 

[csbin]

Ryzen Threadripper on Area-51 boosts to 3.8GHz

 

[lolfail9001]

Ryzen Threadripper on Area-51 boosts to 3.8GHz

Uhm, windows task manager is the worst clock measuring tool in existence.

The curious part is that "maximum clock" thingy. Looks like someone's hopes of TR clocks were crushed hard.

 

[tamz_msc]

Uhm, windows task manager is the worst clock measuring tool in existence.

The curious part is that "maximum clock" thingy. Looks like someone's hopes of TR clocks were crushed hard.

3.4GHz was exactly what was being hinted at from the Blender demo. Though I agree that task manager is no good at measuring CPU clock frequency.

 

[Glo.]

Uhm, windows task manager is the worst clock measuring tool in existence.

The curious part is that "maximum clock" thingy. Looks like someone's hopes of TR clocks were crushed hard.

Engineering Samples for 16C/32T CPU are 3.4/3.7 GHz. So 3.8 GHz would be with... XFR.

https://videocardz.com/69760/engineering-sample-update
Name:
AMD ZD1840A8UGAF4 16/32 3400 3700

Its the exact CPU engineering sample in that screen.

 

[Glo.]

IPC with this clock speed is exactly Haswell/Broadwell level.

 

[cbn]

Well, if the hints in AT article about those ASRock X399 boards and elsewhere are anything to go by, this 4000 contact LGA socket is going to be expensive. And part of that must be because of volume. So one way to get the socket price down for both TR and Epyc is surely to sell more boards. If an 8C part with at least some extra features increases the volume the price for TR and Epyc boards comes down. However, the extra PCIe lanes and memory channels on a dual die package implies a 2+2 & 2+2 to reach 8C which with the rumoured 80% yields means they will most likely have to cripple perfectly good parts.

True but they are probably doing that already with Ryzen 5. They where clever enough to give the quads lower frequency. I bet the 1400 is mostly here to salvage dies with bad voltage/frequency curve (but not necessarily broken chips).

Another thing AMD could do (I think) is use what would have been two Athlon x 4 processors (ie, Raven Ridge with defect in iGPU) and MCM them together. This would decrease the PCIe lanes* though.

So entry level could be 8C/16T with less PCIe lanes (using two harvested Raven Ridge) and 8C/16T with greater PCIe lanes (using two harvested Summit Ridge).

*Assuming Raven Ridge follows the trend set by Bristol Ridge where the APU dies have less PCIe lanes.

 

[X499-24c]

The reason AMD kept the same package size and pin count for Threadripper and EPYC isn't just for economics of scale sake, but also for the sake of flexibility to counter Intel's responses. And so they will. For the past couple of years AMD has been doing their best to keep their ability to respond open, so quick and rushed maneuvering from Intel, as witnessed with the announcement of the 18 core HEDT option before Intel is even sure what kind of specifications it will have, will not be able to catch AMD off guard and without the ability to retaliate.

AMD has setup the core wars to be in their favor for the next couple of years. This is information for 2000 series Threadripper coming next year to X399 and X490/X499.

The extra package space available to Threadripper will be utilized next year to create a Tri-Pinnacle Ridge MCM for the platform. They will come in 12 core, 18 core, and 24 core flavors. While they will slot into existing motherboards with a BIOS update, only the extra cores will be of benefit. For the extra I/O afforded by another Pinnacle die (6 channel and 96 PCI-E lanes), motherboards would need to be new. They have the available pins, but they're not setup for it. One of the dies can also be disabled for a 16 core option.


All of the above I confirmed from my sources to be happening. From here on out, this information is still under debate inside AMD for the best course of action, or depends on hitting certain performance targets.

Platform: There is the debate of whether it's worth to create another HEDT platform even higher than X399. In such a case, there would be quad channel 64 lane X490 (X399 refresh), and hexa channel 96 lane X499. These X499 motherboards would be incredibly expensive, but would allow AMD to increase dominance over Intel in the HEDT space in every way, not just core count.

There is also the question of higher TDP headroom, as three Pinnacle Ridge dies would need more headroom than the current X399 is rated for to hit the intended clock ranges.

Performance: Pinnacle Ridge will be higher clocking and more efficient die at the higher end of the clock spectrum, though it will remain about the same efficiency wise in the 3GHz range. Slightly larger, but still under 200mm^2. For this reason, the 18 core variant should clock higher than 16 core Threadripper while staying within X399's TDP limits. I am told to expect 4.4GHz XFR or thereabouts for the most expensive 18 core SKU, with base clocks in the range of 3.8GHz to 4GHz.

For the 24 core SKU, X399's TDP limits will not suffice to run at the higher end of the clocking spectrum. There is the debate of whether to make it exclusive to X499, and potentially X490 if TDP limits are raised to accomodate, or allow it to run on X399/X490 with a reduced clock profile when on these machines (Which can be overriden with overclocking).

Pricing: AMD hopes to remain aggressive in pricing should market conditions allow them. Current targets are 1200$ for the top 18 core, and about 1800$ for 24 cores. These prices are subject to change as the products are far enough away for Intel to have a chance to re-organize their pricing by launch.

Timing: Should all go well, AMD is looking at around early Q2 2018 for 18/12 core on X399, and late Q3 2018 for 24 core Threadripper 2000 parts, with a showing at Computex of X490/X499 and the lineup.

 

[cbn]

Do you guys think this will have better gaming performance because of the quad channel memory config?

That is a good question.

If it doesn't now, then I expect it probably would in the future.

 

[nathanddrews]

All of the above I confirmed from my sources to be happening.

Who are your sources?

 

[X499-24c]

Who are your sources?

Friends at AMD is all I can say.

I've known about this for a while, but now multiple friends are saying the same thing, so I feel confident in posting this.

 

[cbn]

The reason AMD kept the same package size and pin count for Threadripper and EPYC isn't just for economics of scale sake, but also for the sake of flexibility to counter Intel's responses. And so they will. For the past couple of years AMD has been doing their best to keep their ability to respond open, so quick and rushed maneuvering from Intel, as witnessed with the announcement of the 18 core HEDT option before Intel is even sure what kind of specifications it will have, will not be able to catch AMD off guard and without the ability to retaliate.

AMD has setup the core wars to be in their favor for the next couple of years. This is information for 2000 series Threadripper coming next year to X399 and X490/X499.

The extra package space available to Threadripper will be utilized next year to create a Tri-Pinnacle Ridge MCM for the platform. They will come in 12 core, 18 core, and 24 core flavors. While they will slot into existing motherboards with a BIOS update, only the extra cores will be of benefit. For the extra I/O afforded by another Pinnacle die (6 channel and 96 PCI-E lanes), motherboards would need to be new. They have the available pins, but they're not setup for it. One of the dies can also be disabled for a 16 core option.


All of the above I confirmed from my sources to be happening. From here on out, this information is still under debate inside AMD for the best course of action, or depends on hitting certain performance targets.

Platform: There is the debate of whether it's worth to create another HEDT platform even higher than X399. In such a case, there would be quad channel 64 lane X490 (X399 refresh), and hexa channel 96 lane X499. These X499 motherboards would be incredibly expensive, but would allow AMD to increase dominance over Intel in the HEDT space in every way, not just core count.

There is also the question of higher TDP headroom, as three Pinnacle Ridge dies would need more headroom than the current X399 is rated for to hit the intended clock ranges.

Performance: Pinnacle Ridge will be higher clocking and more efficient die at the higher end of the clock spectrum, though it will remain about the same efficiency wise in the 3GHz range. Slightly larger, but still under 200mm^2. For this reason, the 18 core variant should clock higher than 16 core Threadripper while staying within X399's TDP limits. I am told to expect 4.4GHz XFR or thereabouts for the most expensive 18 core SKU, with base clocks in the range of 3.8GHz to 4GHz.

For the 24 core SKU, X399's TDP limits will not suffice to run at the higher end of the clocking spectrum. There is the debate of whether to make it exclusive to X499, and potentially X490 if TDP limits are raised to accomodate, or allow it to run on X399/X490 with a reduced clock profile when on these machines (Which can be overriden with overclocking).

Pricing: AMD hopes to remain aggressive in pricing should market conditions allow them. Current targets are 1200$ for the top 18 core, and about 1800$ for 24 cores. These prices are subject to change as the products are far enough away for Intel to have a chance to re-organize their pricing by launch.

Timing: Should all go well, AMD is looking at around early Q2 2018 for 18/12 core on X399, and late Q3 2018 for 24 core Threadripper 2000 parts, with a showing at Computex of X490/X499 and the lineup.

Why not just go straight to octa-channel and 32C/64T? (ie, four packages). It does share the same pin count right?

Then have an option for 24C.

Form factor: EATX for 16 DIMM slots and ATX for eight DIMM slots.

 

[X499-24c]

Why not just go straight to octa-channel and 32C/64T? (ie, four packages). It does share the same pin count right?

Then have an option for 24C.

Form factor: EATX for 16 DIMM slots and ATX for eight DIMM slots.

Cannibalization of Naples/EPYC is the main concern. Neither Intel nor AMD want to edge too close to their top offerings. Even 24 cores for HEDT is highly aggressive.

In fact the main reason the 24 core offering will come later than the 18 core offering is simply to minimize the time before HEDT gets 24 cores and datacenters get 36+ cores. This can change depending on Intel's actions, but AMD hopes to minimize time between the two.

 

[T1beriu]

This "leak" doesn't make any technical or economical sense.

They kept the EPYC socket so they can achieve 18 & 24 cores on TR. But.... wait for it... they need a new platform to achieve this, segmenting the HEDT platform into regular and ULTRA HEDT, an already niche segment that doesn't sell many CPUs, but they create a niche within a niche and, apparently, AMD has tons of money since they can develop so many new platforms in such a short time.

A new platform that they will launch just a year after they released the new X399 one.

Nice try dude. You need to work harder on your "speculative leaks".

Probably this guy is from a fake news click bait publication like w-junk-tech that need a "leak" posted somewhere so they can write 20 articles about it and get rich while doing it.

 

[X499-24c]

This "leak" doesn't make any technical or economical sense.

They kept the EPYC socket so they can achieve 18 & 24 cores on TR. But.... wait for it... they need a new platform to achieve this.

A new platform that they will launch a year after they just released a new one.

Nice try dude. You need to work harder on your "speculative leaks".

Probably this guy is from a fake news click bait publication like w-junk-tech that need a "leak" posted somewhere so they can write 20 articles about it and get rich while doing it.

The need is strictly for TDP reasons. Otherwise the existing platform can easily accept 24 cores at lower clocks.

The split into HEDT and "Ultra HEDT" as you call it makes sense from a motherboard cost perspective. 6 channels and 96 PCI-E lanes raises costs significantly from the 4 channels and 64 lanes expected of X399 boards.

 

[coercitiv]

Why not just go straight to octa-channel and 32C/64T? (ie, four packages). It does share the same pin count right?

A new account is created, posts the same info in 2 different threads on this forum, makes no effort to establish even basic credibility for itself or it's sources, yet you engage it and help it create a dialogue on the exact info it is trying to disseminate.

Days later this crap ends up on some click bait site with forum conversations as source, and all AMD threads end up polluted with even more junk.

And look what Google cache came up with: https://webcache.googleusercontent....s-more-up-its-sleeve-to-counter-x299.2508498/

Apparently, from the moment the new user "ButWaitThere'sMore" attempted to post on a new thread until user "X499-24c" finally posted the info again, new details came to light, as the improved version of the post contains a more detailed timeline.

 

[cbn]

A new account is created, posts the same info in 2 different threads on this forum, makes no effort to establish even basic credibility for itself or it's sources, yet you engage it and help it create a dialogue on the exact info it is trying to disseminate.

What didn't you like about my question?

 

[cbn]

The need is strictly for TDP reasons. Otherwise the existing platform can easily accept 24 cores at lower clocks.

The split into HEDT and "Ultra HEDT" as you call it makes sense from a motherboard cost perspective. 6 channels and 96 PCI-E lanes raises costs significantly from the 4 channels and 64 lanes expected of X399 boards.

The socket is the same.....so it can power up 2, 3 or 4 dies.

The only change that needs to happen is AMD releasing unlocked processors with more than 16C/32T.

P.S. 24C from four harvested (ie, lower quality) dies probably makes a lot more sense to AMD than using three perfect dies. This even before factoring in the reduced memory channels and DIMM slots.

 

[coercitiv]

What didn't you like about my question?

You enable the conversation, and help the other party establish credibility. Your choice ofc.