The Future of Silicon: An Exclusive Interview with Dr. Gary Patton, CTO of GlobalFoundries

[raghu78]

https://www.anandtech.com/show/1243...ew-with-dr-gary-patton-cto-of-globalfoundries

Excellent article. Key takeaways.

1. 12LP is a partial optical shrink . MOL and BEOL specifically. I am very confident that my earlier guess of 12LP MMP of 56 nm (same as 12 FDX) is going to be true.
2. 7LP extremely competitive with other foundry offerings on performance. GF targetting first source business at 7nm.
3. 7LP HVM targetted for early 2019 with a couple of key partners. AMD is surely one. Who is the other ? QCOM ?
4. 7LP+ with EUV will bring a shrink like 12LP along with performance improvements. My guess is MMP of 36nm down from 40nm at 7LP. I think we will see products built at 7LP+ in H2 2020.
5. GF's next node will deliver huge improvements in power, perf, area like 14nm to 7nm. Gary Patton thinks a big perf boost from 7nm will require a new device architecture. I think GF will have a 4nm GAAFET node with a 55-60% shrink in HVM in 2022. Samsung has already confirmed GAAFET based 4LPP.
6. 22FDX designed specifically from the ground up for IoT/mobile/automotive. Industry leading RF performance which is critical for the target markets. 22FDX can get quite close to 14nm for performance and the next gen 12 FDX can get quite close to 7nm. FD-SOI is ideal for small chips < 150 sq mm where wiring capacitance is not an issue while FINFET is targetted for larger chips which need high drive current and have tons of wiring capacitance.

 

[ao_ika_red]

7LP HVM targetted for early 2019 with a couple of key partners. AMD is surely one. Who is the other ? QCOM ?

IBM nextgen POWER CPU, because GF's 7nm is pretty much developed by IBM engineers before their foundry was handed to GF and on the handover clause GF ought to serve IBM first.

 

[DisEnchantment]

You missed this ...

It is a big performance boost - we quoted around 40%. I don't know how that exactly will translate into frequency, but I would guess that it should be able to get up in the 5GHz range, I would expect.

 

[CatMerc]

I sure hope so. I want a do over for the 9590

 

[Lodix]

Qualcomm has a foundry partnership with Samsung. If they need another source ( next year ) they will use TSMC instead.

 

[Tuna-Fish]

IBM nextgen POWER CPU, because GF's 7nm is pretty much developed by IBM engineers before their foundry was handed to GF and on the handover clause GF ought to serve IBM first.

IBM's next gen CPU is going to be made with 7HP.

 

[ao_ika_red]

IBM's next gen CPU is going to be made with 7HP.

Q4: For 14nm, IBM has its own tweaked variant called 14HP. Is this going to be the case for 12nm or 7nm?

GP: We will give them a high performance version on 7nm, and in exchange, they keep helping us with the research, which is becoming pretty challenging.

Q14: Will GlobalFoundries 7nm have different processes focused on high performance, on mobile, and on low power?

GP: We use different libraries [in the same process]. Libraries are optimized differently, so we have one that is a 2 fin library, so it is ultra-dense, and another that is a 4 fin library for maximum performance. The other thing we did different to some of the other players is that we built a lot of flexibility into our back end, so where there is high performance computing, there is a place where you're going to want to run wider lines and they can do that; we have a place where you can put larger vias, and they can do that. So where IR drop is an issue on a critical path, they can do that with the way we designed our back end line.

Q18: So you would do a custom version of 7LP for IBM, who is currently running 5.2GHz on its 10 core chips - could you also perhaps translate that 40%?

GP: I'm not a system guy so I wouldn't want to commit IBM to it! But certainly, we are very focused on delivering to IBM the performance they need for the next generation, for power and integration into systems. Some of us have worked with them for many years, so we have a good understanding of what they need.

https://www.anandtech.com/show/1155...nm-plans-three-generations-700-mm-hvm-in-2018

Basically, for IBM it will be customised (high performance) version of 7LP (leading performance) so it still counts as 7LP.

 

[NostaSeronx]

Basically, for IBM it will be customised (high performance) version of 7LP (leading performance) so it still counts as 7LP.

It is called 7LP-HPC, which is the High Performance package for 7LP. The Mobile package is called 7LP-SoC, then there is 7LP-ULP which uses 5 track/1 fin, etc.

But if you looked at GlobalFoundries' EUV and IBM's EUV process...
From: A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels

We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm ... ever reported in FinFET technology.

From: Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

In this paper, for the first time we demonstrate that horizontally stacked gate-all-around (GAA) Nanosheet structure is a good candidate for the replacement of FinFET... Good electrostatics are reported at Lg=12nm and aggressive 44/48nm CPP (Contacted Poly Pitch) ground rules.
They offer excellent electrostatics and short channel control, can be fabricated with minimal deviation from FinFET, and circumvent some of the patterning challenges associated with scaled technologies.

Which leads me to believe that 7HP might be a thing if it is the FinFET converted to Nanosheets process. Relaxed 7nm FinFET process => Stacked Nanosheet process is simple in EUV and DUV. For the reason it is relaxed for the FinFET portion means the Nanosheet process would get higher yields. Than if it was just the standard FinFETs in the same node generation. With that they could then make the most bottom nanosheet a dummy in which to bias the above nanosheets. Thus, in theory getting FDSOI capabilities with little effort of change from bulk FinFET design.

 

[ao_ika_red]

I believe GAAFET is still in its infancy and according to this article:
https://semiengineering.com/transistor-options-beyond-3nm/
FinFET will also be used on 5nm process.

 

[raghu78]

It is called 7LP-HPC, which is the High Performance package for 7LP. The Mobile package is called 7LP-SoC, then there is 7LP-ULP which uses 5 track/1 fin, etc.

But if you looked at GlobalFoundries' EUV and IBM's EUV process...
From: A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels

From: Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET


Which leads me to believe that 7HP might be a thing if it is the FinFET converted to Nanosheets process. Relaxed 7nm FinFET process => Stacked Nanosheet process is simple in EUV and DUV. For the reason it is relaxed for the FinFET portion means the Nanosheet process would get higher yields. Than if it was just the standard FinFETs in the same node generation. With that they could then make the most bottom nanosheet a dummy in which to bias the above nanosheets. Thus, in theory getting FDSOI capabilities with little effort of change from bulk FinFET design.

Gary Patton has stated that the next node for them will likely involve a move to GAAFET. I think GF's next node will likely be 3nm and arrive in 2022, 3 years after 7LP. Gary stated that they want to move to nodes which offer a big performance and density increase. I think the recent IMEC 3nm specs look quite realistic for GF's next node.

https://semiengineering.com/wp-content/uploads/2018/02/nextgenfig4png.png

We could see a 3nm node with CPP=40nm (SADP limit) and MMP=26nm (1D EUV limit) with 4T libraries for high density and 6T for high performance. We saw GF 7SoC 6T (CPP=56nm MMP=40nn) provide a 70% shrink from 14LPP 9T (CPP=78nm MMP=64nm) . 3nm with CPP=40nm MMP=26nm 4Twill provide a similar 70% shrink from
7LP 6T (CPP=56nm MMP=40nm)

3nm Cell area = 40 x 26 x 4 = 4160
7LP Cell area = 56 x 40 x 6 = 13440
4160/13440 = 0.309% . So 69% shrink

I believe GAAFET is still in its infancy and according to this article:
https://semiengineering.com/transistor-options-beyond-3nm/
FinFET will also be used on 5nm process.

GAAFET has already been demonstrated in test chips and there will be 4+ years time from when IBM,GF,Samsung first demonstrated working test chips to high volume production.

https://www-03.ibm.com/press/us/en/pressrelease/52531.wss
https://www.researchgate.net/public...nd_transistor_to_enable_scaling_beyond_FinFET

Samsung has already confirmed their 4LPP node is based on GAAFET and will enter risk production in 2020 (mostly late 2020 given their current node cycles) and be in HVM by late 2021.

https://www.techpowerup.com/233696/samsung-announces-comprehensive-process-roadmap-down-to-4-nm
http://www.businesskorea.co.kr/english/news/ict/18182-keeping-innovation-samsung-electronics-announces-world’s-first-4-nano-processing