Question Taiwan Report: Intel has reached an agreement with TSMC

[mikegg]

Mods: if this is true, it should deserve its own thread. If it's not true, please feel free to delete it.

https://m.hexus.net/business/news/components/144379-amd-intel-battle-tsmc-capacity-says-report/

Insiders talking to the Taiwanese newspaper have indicated the following:

• Intel has reached an agreement with TSMC
• TSMC will begin mass production of Intel CPUs and/or GPUs next year
• Intel chips will be fabricated on TSMC's 7nm optimised version of its 6nm process. (I'm not sure if that means TSMC N7P, N7+, or N6.)

No details on the agreement has come out.

My personal predictions on an agreement:

TSMC sees this as an opportunity to force Intel out of the race for bleeding-edge nodes. TSMC will probably allow Intel to keep its 10nm and above nodes since those aren't a threat to them. TSMC may allow Intel to finish its 7nm nodes as well because let's be honest, Intel releasing its 7nm node in the year 2022/2023 is not a threat to TSMC. Intel will stop developing a node below 7nm after signing an agreement with TSMC. Over the next 5 years or so, Intel will sell off all of its existing fabs and become fabless. Intel has no leverage in this deal and TSMC will use this opportunity to completely remove Intel as a threat.

This is just pure speculation but I think Intel did negotiate with Samsung to use a partnership with Samsung as a leverage point in a deal with TSMC. But ultimately, Intel knows going with TSMC is guaranteed access to the best node. In addition, Intel knows signing with TSMC is a punch to Nvidia and two punches to AMD.

 

[DrMrLordX]

Doesn't Intel need N5 for that Aurora super computer contract? They're over a barrel then. The 7nm mix is probably just a bluff to try and obscure how over a barrel TSMC really has them. If it comes out on 7nm, I think it will be well past the deadline.

You are likely correct. N5 is a known-good node that will work once Intel ports their designs over to it. At the present, Intel has Ponte Vecchio as using some chips from their own 7nm and 10nm processes, which means its a multi-chip solution. For something that has to work and work in volume, I can see them moving the 7nm chips over to N5 and the 10nm chips over to N6.

 

[Hitman928]

You are likely correct. N5 is a known-good node that will work once Intel ports their designs over to it. At the present, Intel has Ponte Vecchio as using some chips from their own 7nm and 10nm processes, which means its a multi-chip solution. For something that has to work and work in volume, I can see them moving the 7nm chips over to N5 and the 10nm chips over to N6.

Do we know how big the PV dies are going to be? Last I heard the 5 nm yields were still really bad for large dies, though that was 6+ months ago. I imagine they'd improve significantly by the time PV is launching but if it's a really large die, it might still not yield very well.

 

[DrMrLordX]

Do we know how big the PV dies are going to be? Last I heard the 5 nm yields were still really bad for large dies, though that was 6+ months ago. I imagine they'd improve significantly by the time PV is launching but if it's a really large die, it might still not yield very well.

No clue. My guess is not very large since they're going multi-die, but I could be wrong. If you think N5 is going to have problems with chips near the reticle limit, imagine what Intel 7nm is going to be like . . .

 

[Hitman928]

No clue. My guess is not very large since they're going multi-die, but I could be wrong. If you think N5 is going to have problems with chips near the reticle limit, imagine what Intel 7nm is going to be like . . .

I'm not even talking near the reticle limit, more like 200 mm^2 die.

 

[Doug S]

You are likely correct. N5 is a known-good node that will work once Intel ports their designs over to it. At the present, Intel has Ponte Vecchio as using some chips from their own 7nm and 10nm processes, which means its a multi-chip solution. For something that has to work and work in volume, I can see them moving the 7nm chips over to N5 and the 10nm chips over to N6.

Intel can continue making the 10nm dies itself (those would be the I/O chip) since that process works. Maybe not as well as they like, but they will be able to get all the chips they need out of it. It is the ones currently targeted for Intel 7nm that will have to move to TSMC N5 to be feasible.

 

[Doug S]

I'm not even talking near the reticle limit, more like 200 mm^2 die.

It is quite possible Apple will have some dies in that size range made by TSMC for shipment in products before the end of the year (i.e. the new Macs)

A process that had problems with 200 mm^2 could never produce the tens of millions of chips in the 100 mm^2 range that they've already had to have produced for Apple to be shipping iPhones in a couple months, so that's not even worth worrying about.

A brand new process may have problems making dies near the reticule limit early on, but by the time Intel would need PV wafers it should not be a problem.

 

[chrisjames61]

Maybe because they don't know all that much about the donwsides of SV like insane living cost, traffic jams and general mediocre quality of life. If you go work somewhere in the midwest with half the salary but much better quality of life and getting a house with a football field of land for the same price as a one bed-room in SV.
I see it here as well. Some forgeiners come mostly due to the seemingly high wages and when they realize the living costs, they realize they aren't really off much better.

Really? Have you talked to any? Sounds totally anecdotal.

 

[Hitman928]

It is quite possible Apple will have some dies in that size range made by TSMC for shipment in products before the end of the year (i.e. the new Macs)

A process that had problems with 200 mm^2 could never produce the tens of millions of chips in the 100 mm^2 range that they've already had to have produced for Apple to be shipping iPhones in a couple months, so that's not even worth worrying about.

A brand new process may have problems making dies near the reticule limit early on, but by the time Intel would need PV wafers it should not be a problem.

Haven't Apple's SOCs typically been under 100 mm^2? That size chip has decent yields from what I understand, but as you get around 200 mm^2 and up, it gets really bad. I don't know if it has to do with chip fragility or something but I know (at the time at least) the yield curve by size was much sharper than you'd expect from past nodes.

 

[chrisjames61]

You missunderstood me. Of course people value different things differently. That was exactly my point. The fact you don't have US applicants doesn't mean there aren't any, it can mean that, but it can also mean they prefer different locations. That's all I was pointing out.

The thing is that the US doesn't have anywhere near enough qualified people in most fields of science. We can't fill these positions without H1B visa applicants.

 

[Thunder 57]

The thing is that the US doesn't have anywhere near enough qualified people in most fields of science. We can't fill these positions without H1B visa applicants.

If that is true, we have a serious teaching problem. As for college, maybe stop the "feel good" majors or ones that are nonsense like underwater basket weaving. I think someone said "Sputnik moment?. Yea, we could use one of those again.

 

[Doug S]

Haven't Apple's SOCs typically been under 100 mm^2? That size chip has decent yields from what I understand, but as you get around 200 mm^2 and up, it gets really bad. I don't know if it has to do with chip fragility or something but I know (at the time at least) the yield curve by size was much sharper than you'd expect from past nodes.

They've ranged in size from 80 to around 120, but the 'X' ones for the iPad have been as large as 150.

Without any redundancy (which any good design will have where possible) the defect rate is proportional to area. Double the area, double the bad dies. If going from 100 to 200 mm^2 is a big problem, your yield at 100 is terrible and Apple is going to be very very pissed off at you.

 

[lobz]

If that is true, we have a serious teaching problem. As for college, maybe stop the "feel good" majors or ones that are nonsense like underwater basket weaving. I think someone said "Sputnik moment?. Yea, we could use one of those again.

Forget it. Everybody's a life coach now, fully prepared to be offended by anything.

 

[Thala]

They've ranged in size from 80 to around 120, but the 'X' ones for the iPad have been as large as 150.

Without any redundancy (which any good design will have where possible) the defect rate is proportional to area. Double the area, double the bad dies.

The last sentence is certainly not correct. The number of bad dies more than double if the area doubles.

 

[Hitman928]

They've ranged in size from 80 to around 120, but the 'X' ones for the iPad have been as large as 150.

Without any redundancy (which any good design will have where possible) the defect rate is proportional to area. Double the area, double the bad dies. If going from 100 to 200 mm^2 is a big problem, your yield at 100 is terrible and Apple is going to be very very pissed off at you.

The quotes I heard were < 100mm^2 and you are good at 80+% yields. Large dies (over 200 mm^2) and you start to get really bad yields, as low as 30%.

Edit: obviously the quoted numbers leave a lot of room for interpretation, under 100mm^2 could mean 90 mm^2 or it could mean 50 mm^2 for the quoted yields. I probably lean towards the lower number given the bad yields told to me at the high end. Again, this wasn't a very recent discussion I had so I'm sure things have improved since then, I just don't know by how much.

 

[Hitman928]

The last sentence is certainly not correct. The number of bad dies more than double if the area doubles.

I think it's more accurate to say that the number of good dies is more than doubled when you cut the area in half. You'll probably actually have fewer bad dies per wafer as your die area increases because you just get fewer dies per wafer overall.

It would make sense that you get more than double bad dies per required number of good dies as you'll obviously be burning through more wafers to get there.

 

[Thala]

The last sentence is certainly not correct. The number of bad dies more than double if the area doubles.

I think it's more accurate to say that the number of good dies is more than doubled when you cut the area in half. You'll probably actually have fewer bad dies per wafer as your die area increases because you just get fewer dies per wafer overall.

It would make sense that you get more than double bad dies per required number of good dies as you'll obviously be burning through more wafers to get there.

I was thinking about my last statement and it is not correct either. The correct statement is: The probability of a good die decreases by a factor e^lambda when doubling the die size, where lambda is the average defects per die of the smaller die. So it is highly dependent on the defect rate lambda.

Example: If the average number of defects per die of size A is 1/2, then probability of a good die is e^-1/2=0.61 (or 61% yield). When doubling the die size the probability of a good die is e^-1=0.37 (or 37% yield). Apparently the quotient of yields is 0.61/0.37 = 1.64 = e^1/2.

Background: the number of defects per die is Poisson distributed.

 

[beginner99]

The thing is that the US doesn't have anywhere near enough qualified people in most fields of science. We can't fill these positions without H1B visa applicants.

I'm not US but they are claiming same thing here: We need foreigners to fill "expert" positions. The problem isn't lack of exports, it's lack of pay here (well can't say that for SV). In a country that usually pays higher salaries than US, in tech you will make about half of SV-salaries if not less. That's why I'm generally a little skeptical about this "lack of expert" thing. You need to be a software dev knowing 10 languages as expert, do some devops and then also have data science skills than that for a cool 100k. Yeah, guys you probably find 1000 people in the world that could do that and yeah non will do it for just 100k. Getting foreigners and claiming lack of experts sadly often is just a way to push wages down.

 

[DrMrLordX]

I'm not even talking near the reticle limit, more like 200 mm^2 die.

We'll see. I don't know how large any of the dice will be for Ponte Vecchio, but something tells me it would be unlikely that any such restrictions would last for too much longer if TSMC seriously intends to sell N5 wafers to customer like AMD (whom they are allegeldy pressuring to take wafers ASAP).

Intel can continue making the 10nm dies itself (those would be the I/O chip) since that process works. Maybe not as well as they like, but they will be able to get all the chips they need out of it. It is the ones currently targeted for Intel 7nm that will have to move to TSMC N5 to be feasible.

They could, if they have the volume. We still don't know Intel's yields on 10nm for 4c Tiger Lake, much less anything else on 10nm. Intel apparently ordered a pretty massive number of N6 wafers from TSMC. Those wafers gotta be for something. You know a guy like Koduri is probably going to try to get shipping (versus test case) Ponte Vecchio on TSMC wafers to the greatest extent possible.

The thing is that the US doesn't have anywhere near enough qualified people in most fields of science. We can't fill these positions without H1B visa applicants.

That's never been proven.

Getting foreigners and claiming lack of experts sadly often is just a way to push wages down.

The real issue is that American companies don't want to train American college graduates to work for American wages. They'll take an H1B applicant with falsified credentials, pay an American for a few extra weeks/months to train said H1B applicant (before laying off the American), and then set the H1B loose and hope for the best. They can always toss the guy and get him deported if they need to put out feelers for more cannon fodder. I honestly don't know how many H1Bs work for Intel, but what kind of people do you suppose work at TSMC? Here's a hint: not the guys getting H1Bs to work in the States.

 

[pike55]

Lastly, TSMC will never sink. If the U.S. government cuts off TSMC, governments and investors around the world will be more than happy to invest in TSMC to keep it afloat while it transitions away from fabbing for U.S. chipmakers.
It does mean the end of the U.S. semiconductor industry though, maybe even the U.S. computing industry in general.

There is no need for the U.S. to cut off TSMC.
Taiwan (and therefore TSMC) 's life / existance depends on the U.S. politically / military protecting it against china. And no other investors / countries can take over that job.
TSMC following U.S. orders to stop suplying Huawei is an example. (And coincidence: there are U.S. companies to take over that capacity ...)
Imho TSMC alone is a big enough reason for the U.S. to prevent any kind of "reunification" of China and Taiwan anytime soon.
---
What hasn't been asked in this thread is the possibility for Intel to just license a process from TSMC?
Similar to Global Foundaries a few years ago (from Samsung).
That way Intel could use their existing fabs, can get the capacity they need and TSMC gets a big chunk of extra money.
Probably Intel won't get the latest process nodes from TSMC or at least with some delay, but even then it would be much better for Intel than their current and forseeable future situation.

 

[Thibsie]

I dunno if Intel is ready to swallow that one. I don't think so.
TSMC would probably require intel not to compete.

 

[amd6502]

I dunno if Intel is ready to swallow that one. I don't think so.
TSMC would probably require intel not to compete.

That seems doable; they probably only fab their own products anyway (or at least mostly so).

Imho TSMC alone is a big enough reason for the U.S. to prevent any kind of "reunification" of China and Taiwan anytime soon.

That's not going to happen anyway, at least for many generations to centuries. Reunification would surely require popular vote from both Taiwan and China, and the PRC is unpopular in Taiwan (and China won't let ROC enter/compete in mainland politics).